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advance cyw43570 single-chip 5g wifi ieee 802.11ac 22 mac/baseband/radio with integrated bluetooth 4.1 and edr cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-15054 rev. *i revised october 27, 2016 the cypress cyw43570 is a complete dual-band (2.4 ghz and 5 g hz) 5g wifi 2 2 mimo mac/ phy/radio system-on-a-chip. this wifi single-chip device provides a hi gh level of integrat ion with a d ual-stream ieee 802.11ac ma c/baseband/radio and bluet ooth 4.1 + enhanced data rate (edr). in ieee 8 02.11ac mode, the wlan operation supports rates of mcs0?mcs9 (up to 256 qam) in 20 mhz, 40 mhz, and 80 mhz channels for data rates up to 867 mbp s. in addition, all the ieee 80 2.11a/b/g/n rates are supported. included on-chip are 2.4 ghz and 5 ghz transmitter pow er amplifiers and receiver low noise amplifiers. the cyw43570 integrates several peripheral interfaces including usb 2.0 (bluetooth), pcie (wi-fi), and serial flash. for the bluetooth section, the host interface options are a high-speed 4-wire uart and usb 2.0 full-speed (12 mbps). the cyw43570 uses advanced design techniques and process technology to reduce active and idle power, and includes an embedded power mana gement unit that simplifies the system power topology. the cyw43570 implements highly sophisticated enhanced collaborati ve coexistence hardware mechanisms and algorithms that ensure that wlan and bluetooth collaboration is optimized for maximum performance. this datasheet provides details on the func tional, operational, and electrical charac teristics for the cypress cyw43570. it is intended for hardware design, application, and oem engineers. cypress part numbering scheme cypress is converting the acquired iot part nu mbers from broadcom to the cypress part numbering scheme. due to this conversion, there is no change in form, fit, or functi on as a result of offering the device with cypress part number marking. the table pro vides cypress ordering part number that matches an existing iot part number. figure 1. functional block diagram for pcie (wlan) and bt (usb 2.0) interfaces table 1. mapping table for part number between broadcom and cypress broadcom part number cypress part number bcm43570 cyw43570 BCM43570KFFBG cyw43570kffbg t/r ? switch diplexer vio vbat ? ** 5g ? wlan cyw43570 wlan ? host ? i/f bluetooth ? host ? i/f wl_reg_on pcie bt_reg_on uart* bt_dev_wake* ? bt_host_wake* i 2 s* bt_vsync_in pcm usb ? 2.0 bt ant1 t/r ? switch 5g ? wlan ant0 wl_host_wake xtal ? 40 ? mhz * not available in the p1xx design reference board. ** vbat is the main power supply (ranges from 3.0v to 3.6v) to the chip. t/r ? switch 2g ? wlan t/r ? switch 2g ? wlan diplexer
document number: 002-15054 rev. *i page 2 of 94 advance cyw43570 features ieee 802.11x key features ieee 802.11ac draft compliant. dual-stream spatial multiplexing up to 867 mbps data rate. supports 20, 40, and 80 mhz channels with optional sgi (256 qam modulation). full ieee 802.11a/b/g/n legacy compatibility with enhanced performance. tx and rx low-density parity check (ldpc) support for improved range and power efficiency. supports ieee 802.11 ac/n beamforming. on-chip power amplifiers and low-noise amplifiers for both bands. supports various rf front-end architectures including: ? three antennas design: two separate antennas (core0 and core1 to wlan) and a separate antenna to bluetooth. ? optional support: two antennas with wlan diversity and a shared bluetooth antenna. internal fractional npll allows support for a wide range of reference clock frequencies. supports pcie gen2 interface but up to gen1 transfer speed. onedriver? software architecture for easy migration from existing embedded wlan and bluetooth devices as well as future devices. bluetooth key features complies with bluetooth core specification version 4.1 + edr with provisions for supporting future specifications. bluetooth class 1 or class 2 transmitter operation. supports extended synchronous connections (esco), for enhanced voice quality by allowing for retransmission of dropped packets. adaptive frequency hopping (afh) for reducing radio frequency interference. host controller interface (hci) using a usb or high-speed uart interface and pcm for audio data. hci/uart interface capable but not currently supported. usb 2.0 full-speed (12 mbps ) supported for bluetooth. low-power mode helps power consumption of the media devices. supports multiple simultaneous advanced audio distribution profiles (a2dp) for stereo sound. automatic frequency detection for standard crystal and tcxo values. supports serial flash interfaces. general features supports 3.3v power supplies with internal switching regulator. programmable dynamic power management 484 bytes of user-accessible otp for storing board param- eters gpios supported: 16 package: 254-ball fcbga (10 mm 10 mm, 0.4 mm pitch) security: ? wpa and wpa2 (personal) support for powerful encryption and authentication ? aes and tkip in hardware for faster data en cryption and ieee 802.11i compatibility ? reference wlan subsystem provides cisco compatible extensions (ccx, ccx 2.0, ccx 3.0, ccx 4.0, ccx 5.0) ? reference wlan subsystem pr ovides wi-fi protected set- up (wps) worldwide regulatory support: gl obal products supported with worldwide homologated design.
document number: 002-15054 rev. *i page 3 of 126 cyw43570 contents 1. overview ............................................................ 5 1.1 overview ............................................................. 5 1.3 standards compliance ........................................ 7 2. power supplies and power management ....... 9 2.1 power supply topology ..... .............. ........... ........ 9 2.2 cyw43570 pmu features .................................. 9 2.3 wlan power management ............................... 11 2.4 pmu sequencing .............................................. 11 2.5 power-off shutdown ....... .................................. 12 2.6 power-up/power-down/re set circuits ............. 12 3. frequency references ................................... 13 3.1 crystal interface and clock generation ............ 13 3.2 external frequency reference ......................... 14 4. bluetooth overview ........................................ 15 4.1 features ............................................................ 15 4.2 bluetooth radio ................................................. 16 5. bluetooth baseband core.............................. 18 5.1 bluetooth 4.1 features ...................................... 18 5.2 bluetooth low energy ....................................... 18 5.3 link control layer ............................................. 18 5.4 test mode support ....... .............. .............. ......... 19 5.5 bluetooth power management unit .................. 19 5.6 adaptive frequency hoppi ng .............. .............. 22 5.7 advanced bluetooth/wlan coexistence .......... 22 5.8 fast connection (interlaced page and inquiry scans) ................................................... 22 6. microprocessor and memory unit for bluetooth ......................................................... 23 6.1 ram, rom, and patch memory ........................ 23 6.2 reset ................................................................. 23 7. bluetooth peripheral tr ansport unit ............. 24 7.1 spi/uart transport detection ......................... 24 7.2 pcm interface ................................................... 24 7.3 usb interface .................................................... 31 7.4 uart interface ................................................. 32 7.5 i 2 s interface ...................................................... 34 8. wlan global functions................................. 37 8.1 wlan cpu and memory s ubsystem .... ........... 37 8.2 one-time programmable memory .................... 37 9. pci express interface ..................................... 39 9.1 transaction layer interface .............................. 39 9.2 data link layer ..................................................39 9.3 physical layer ....................................................40 9.4 logical subblock .............. ............... ........... ........40 9.5 scrambler/descrambler .....................................40 9.6 8b/10b encoder/decoder ............... ........... ........40 9.7 elastic fifo .......................................................40 9.8 electrical subblock ......... .............. .............. ........40 9.9 configuration space ...........................................40 10. wlan mac and phy ...................................... 41 10.1 ieee 802.11ac draft mac .............. ........... ........41 10.2 ieee 802.11ac draft phy ............... ........... ........44 11. wlan radio subsystem ............................... 45 11.1 receiver path .....................................................45 11.2 transmitter path .................................................45 11.3 calibration ..........................................................45 12. pin diagram and signal descriptions........... 46 12.1 ball maps ...........................................................46 12.2 pin list ...............................................................48 12.3 signal descriptions ............................................51 12.4 wlan/bt gpio signals and strapping options 56 13. dc characteristics.......................................... 57 13.1 absolute maximum rating s ...............................57 13.3 recommended operating conditions and dc characteristics ............................................. 58 14. bluetooth rf specifications .......................... 59 15. wlan rf specifications................................ 62 15.1 introduction ........................................................62 15.2 2.4 ghz band general rf specifications ..........62 15.3 wlan 2.4 ghz receiver performance specifications ..................................................... 63 15.4 wlan 2.4 ghz transmitter performance specifications ..................................................... 67 15.5 wlan 5 ghz receiver performance specifications ..................................................... 68 15.6 wlan 5 ghz transmitter performance specifications ..................................................... 73 16. internal regulator electrical specifications. 74 16.1 core buck swit ching regulator .........................74 16.2 2.5v ldo (btldo2p5) ......................................75 16.3 cldo .................................................................76 16.4 lnldo ...............................................................77
document number: 002-15054 rev. *i page 4 of 126 cyw43570 17. system power consumption ......................... 78 17.1 wlan current consumpti on ............................. 78 17.2 bluetooth current consum ption ........................ 80 18. interface timing and ac characteristics...... 81 18.1 pci express interface pa rameters .................... 81 19. power-up sequence and timing ................... 83 19.1 sequencing of reset and regulator control signals ............................................................... 83 20. package information....................................... 88 20.1 package thermal characteristics ..................... 88 20.2 junction temperature estimation and psi jt versus theta jc .................................................. 88 20.3 environmental characteristics ...........................88 21. mechanical information.. ................................ 89 22. ordering information...................................... 90 23. additional information ................................... 90 23.1 acronyms and abbreviations .............................90 23.2 references .........................................................90 24. iot resources ................................................. 90 document history........................................................... 91 sales, solutions, and legal information ...................... 93
document number: 002-15054 rev. *i page 5 of 94 advance cyw43570 1. overview 1.1 overview the cypress cyw43570 single-chip device provides the highest le vel of integration for a mobile or handheld wireless system, wit h integrated ieee 802.11 a/b/ g/n/ac mac/baseband/radio and bluetooth 4.1 + edr. it provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and f unction. comprehensive power ma nagement circuitry and softw are ensure the system can me et the needs of highly mobile devic es that requir e minimal power consumption and reliable operation. figure 2 shows the interconnect of all the major physical blocks in th e cyw43570 and their associated ex ternal interfaces, which are described in greater detail in the following sections. table 2. device interface support feature interface capability currently supported interfaces bt gpio (bluetooth) yes yes gpio 16 no gpio (wi-fi) yes yes i 2 syesno i 2 s (bluetooth) yes no jtag (wi-fi) yes no pcie (wi-fi) yes yes pcm yes no pcm (bluetooth) yes no spi yes no uart (bluetooth) yes no uart (wi-fi) yes no usb 2.0 (bluetooth) yes yes
document number: 002-15054 rev. *i page 6 of 94 advance cyw43570 figure 2. cyw43570 block diagram cyw43570 bluetooth debug bt ? control ? clock ptu wlan pmu controller 5 ? ghz ? ipa 5 ? ghz 2.4 ? ghz diplexer lna core1 lna 5 ? ghz 2.4 ? ghz lna core0 lna bt ? radio 2x2 ? lcnxnphy 802.11abgn/ac gpio gpio pcie otp sw ? reg ldo lpo xtal ? osc por gpio pcie xtal power ? supply arm jtag axi backplane ram rom bt \ wlan ? eci io ? port ? control uart usb ? i 2 s gpio clock ? management sleep timer pmu pmu ? controller lpo xo ? buffer bt ? phy bt ? rf ram rom patch inter ? ctrl dma bus ? arb wd ? timer sw ? timer gpio ? ctrl apb ahb ahb2 ? apb ? bridge armcr4 etm jtag sdp ahb ? bus ? matrix clb ahb bt ? digital ? io ext ? lna ? rf ? switch ? control usb ? 2.0 smps ? control xtal vbat* vreg bt ? reg ? on 2.4 ? ghz ? ipa 5 ? ghz ? ipa 2.4 ? ghz ? ipa diplexer pcm bt ? host ? wake bt ? dev ? wake 3dg ? vsync ? in 3dg ? vsync ? out wl ? reg ? on por wlan ? host ? wake lna pa note*: ? vbat ? is ? the ? main ? power ? supply ? (ranges ? from ? 3.0v ? to ? 3.6v) ? to ? the ? chip.
document number: 002-15054 rev. *i page 7 of 94 advance cyw43570 1.2 features the cyw43570 supports the following features: ieee 802.11a/b/g/n/ac dual-band 2x2 mimo radi o with virtual-simultan eous dual-band operation bluetooth v4.1 + edr with integrated class 1 pa concurrent bluetooth and wlan operation on-chip wlan driver execution capable of supporting ieee 802.11 functionality wlan host interface, pcie 2.0 (wi-fi), is compatible with gen2 but the interface speed is up to gen1 only. bt host digital interface (can be used concurrently with above interfaces): ? uart (up to 4 mbps) bt supports full-speed usb 2.0-compliant interface enhanced coexistence support, ability to coordi nate bt sco transmissions around wlan receives hci high-speed uart (h4, h4+, and h5) transport (interface capable, but not currently supported) wideband speech support (16 bit linear data, msb first, left justif ied at 4k samples/s for transparent air coding, both through i 2 s and pcm interface). (interface c apable, but not currently supported) bluetooth smartaudio technology improv es voice and music quality to headsets bluetooth low power inquiry and page scan bluetooth low energy (ble) support bluetooth packet loss concealment (plc) bluetooth wideband speech (wbs) 1.3 standards compliance the cyw43570 supports the following standards: bluetooth 2.1 + edr bluetooth 3.0 + hs bluetooth 4.1 + edr ieee802.11ac mandatory and optional requireme nts for 20 mhz, 40 mhz, and 80 mhz channels ieee 802.11n (handheld devi ce class, section 11) ieee 802.11a ieee 802.11b ieee 802.11g ieee 802.11d ieee 802.11h ieee 802.11i
document number: 002-15054 rev. *i page 8 of 94 advance cyw43570 security: ? wep ? wpa personal ? wpa2 personal ? wmm ? wmm-ps (u-apsd) ? wmm-sa ? aes (hardware accelerator) ? tkip (hardware accelerator) ? ckip (software support) proprietary protocols: ? ccxv2 ? ccxv3 ? ccxv4 ? ccxv5 the cyw43570 will support the following future drafts/standards: ieee 802.11r (fast roaming between aps) ieee 802.11w (secure management frames) ieee 802.11 extensions: ? ieee 802.11e qos enhancements (in a ccordance with the wmm specificatio n, qos is already supported.) ? ieee 802.11h 5 ghz extensions ? ieee 802.11i mac enhancements ? ieee 802.11k radio re source measurement
document number: 002-15054 rev. *i page 9 of 94 advance cyw43570 2. power supplies and power management 2.1 power supply topology one buck regulator, multiple ldo regulators, and a power managem ent unit (pmu) are integrated into the cyw43570. all regulators are programmable via the pmu. these blocks si mplify power supply design for bluetooth and wlan func tions in embedded designs. a single vbat 1 (3.0v to 3.6v maximum) and vio supp ly (1.8v to 3.3v) can be used, with all additional voltages being provided by the regulators in the cyw43570. two control signals, bt_reg_on and wl_reg _on, are used to power-up the regulators an d take the respective section out of reset. the cbuck cldo and lnldo power up when any of the rese t signals are deasserted. all regulators are powered down only when both bt_reg_on and wl_reg_on are deasserted. the cldo and lnldo may be turned off/on based on the dynamic demands of the digital baseband. the cyw43570 allows for an extremely lo w power-consumption mode by completely sh utting down the cbuck, cldo, and lnldo regulators. when in this state, lpldo1 and lpldo2 (which ar e low-power linear regulators that are supplied by the system vio supply) provide the cyw43570 with all the voltages it requires, further reducing leakage currents. figure 3 shows a typical power topology. 2.2 cyw43570 pmu features vbat to 1.35vout (550 ma nominal, 870 ma ma ximum) core-buck (cbuck) switching regulator vbat to 2.5v out (15 ma nominal, 70 ma maximum) btldo2p5 1.35v to 1.2vout (100 ma nominal, 150 ma maximum) lnldo 1.35v to 1.2vout (350 ma nominal, 500 ma maxi mum) cldo with bypass mode for deep-sleep additional internal ldos (not externally accessible) 1. vbat is the main power supply (ranges from 3.0v to 3.6v) to the chip.
document number: 002-15054 rev. *i page 10 of 94 advance cyw43570 figure 3. power topology (typical) cyw43570 internal vcoldo internal lnldo internal lnldo internal lnldo xtal ldo lnldo (max. 150 ma) cldo (max. 300 ma) (bypass in deep sleep) btldo2p5 (max. 70 ma) wlan/bt/clb/top, always on wl otp wl phy wl digital bt digital wlan bbpll/dfll pcie pll/rxtx dfe/dfll wl rf ? afe 1.2v wl rf ? tx (2.4 ghz & 5 ghz) 1.2v wl rf ? lo gen (2.4 ghz & 5 ghz) 1.2v wl rf ? rx/lna (2.4 ghz & 5 ghz) 1.2v wl rf ? xtal 1.2v wl rf ? rfpll pfd/mmd bt rf/fm 1.2v 1.2- 1.1v bt class 1 pa wl rf ? pa (2.4 ghz & 5 ghz) wl pad (2.4 ghz & 5 ghz) vddio_rf wl otp (3.3v) wl rf?vco wl rf?cp internal lnldo internal lnldo 2.5v 2.5v 2.5v 1.35v lpldo1 wl_reg_on bt_reg_on wl/bt srams 1.1v core buck regulator cbuck vbat vddio
document number: 002-15054 rev. *i page 11 of 94 advance cyw43570 2.3 wlan power management the cyw43570 has been designed with the stringen t power consumption requirements of mob ile devices in mind. all areas of the chip design are optimized to minimize power consumption. silicon processes and cell libraries were chosen to reduce leakage cur rent and supply voltages. additionally, the cyw43570 integrated ram is a high vt memory with dynamic clock control. the dominant supply current consumed by the ram is leakage current on ly. additionally, the cyw43570 includes an advanced wlan power management unit (pmu) sequencer. the pmu sequencer provides si gnificant power savings by putting the cyw43570 into various power management states appropriate to the current environment and activities that are being performed. the power management unit enables and disables internal regulators, switches, and ot her blocks based on a computation of the required resources and a table that describes the relationship between resources and th e time needed to enable and disable them. power up sequences are fully programmable. configurable, free-running counters (running at 32.768 khz lpo clock) in the pmu sequencer are used to turn on/turn off individual regulators and power switches. clock speed s are dynamically changed (or gated altogether) for the curren t mode. slower clock speeds are used wherever possible. the cyw43570 wlan power states are described as follows: active mode? all wlan blocks in the cyw43570 are powered up and fully functional with active carrier sensing and frame transmission and receiving. all required regulators are enabled and put in the most efficient m ode based on the load current. c lock speeds are dynamically adjusted by the pmu sequencer. doze mode?the radio, analog domains, and most of the linear regulators are powere d down. the rest of the cyw43570 remains powered up in an idle state. all main clocks (pll, crystal oscillator, or tcxo) are shut down to reduce active power to the min imum. the 32.768 khz lpo clock is available only for the pmu sequencer. this condition is necessary to allow the pmu sequencer to wake up the chip and transition to active mode. in doze mode, the primary power consumed is due to leakage current. deep-sleep mode?most of the chip including both analog and digita l domains and most of the regulators are powered off. logic states in the digital core are saved and preserved into a retent ion memory in the always-on domain before the digital core is powered off. upon a wake-up event triggered by the pmu timers, an ex ternal interrupt or a host resu me through logic states in t he digital core are restored to their pre-deep-sleep settings to avoid leng thy hw reinitialization. power-down mode?the cyw43570 is effectively powered off by shutti ng down all internal regulators. the chip is brought out of this mode by external logic re-enabling the internal regulators. 2.4 pmu sequencing the pmu sequencer is responsible for minimizing system power consumption. it enables and disables various system resources based on a computation of the required resources and a table that describes the relationship between resources and the time nee ded to enable and disable them. resource requests may come from several sources: clock requests from cores, the minimum resources defined in the resourcemin register, and the resources requested by any active resource re quest timers. the pmu sequencer maps clock requests into a set o f resources required to pro duce the requested clocks. each resource is in one of four states : enabled, disabled, transition_on, and trans ition_off and has a timer that contains 0 wh en the resource is enabled or disabled and a non-zero value in the tran sition states. the timer is loaded with the time_on or time_off value of the resource when the pmu determines that the resource must be enabled or disabled. that timer decrements on each 32.768 khz pmu clock. when it reaches 0, the state changes from transition_off to disabled or tr ansition_on to enabled. if the time_on val ue is 0, the resource can go immediately from disabled to enabled. sim ilarly, a time_off value of 0 indicates that the resource can g o immediately from enabled to disabled. the terms enable sequence an d disable sequence refer to either the immediate transition o r the timer load-decrement sequence. during each clock cycle, t he pmu sequencer performs the following actions: computes the required resource set based on requests and the resource dependency table. decrements all timers whose values are non zero. if a timer re aches 0, the pmu clears the resourcepending bit for the resource and inverts the resourcestate bit. compares the request with the current resource status an d determines which resources must be enabled or disabled. initiates a disable sequence for each resource that is enabled , no longer being requested, and has no powered up dependents. initiates an enable sequence for each res ource that is disabled, is being reques ted, and has all of its dependencies enabled.
document number: 002-15054 rev. *i page 12 of 94 advance cyw43570 2.5 power-off shutdown the cyw43570 provides a low-power shutdown feature that allows the device to be tu rned off while the host, and any other device s in the system, remain operational. when the cyw43570 is not needed in the system, vddio_rf and vddc are shut down while vddio remains powered. this allows the cyw43570 to be effectively off while keeping the i/o pins powered so that they do not dr aw extra current from any other devices connected to the i/o. during a low-power shut-down state, provided vddio remains applied to the cyw43570, all outputs are tristated, and most inputs signals are disabled. input volta ges must remain within the limits defined for norma l operation. this is done to prevent curren t paths or create loading on any digital signals in the system, and enable s the cyw43570 to be fully integrated in an embedded device a nd take full advantage of the lowest power-savings modes. when the cyw43570 is powered on from this state, it is the same as a normal power-up and the device does not retain any informa tion about its state from bef ore it was powered down. 2.6 power-up/power -down/reset circuits the cyw43570 has two signals (see ta b l e 3 ) that enable or disable the bluetooth and wlan circuits and the internal regulator blocks, allowing the host to control power consumption. for timing diagra ms of these signals and the required power-up sequences, see section 19. power-up sequence and timing . table 3. power-up/power-down/reset control signals signal description wl_reg_on this signal is used by the pmu (with bt_reg _on) to power up the wlan section. it is also or- gated with the bt_reg_on input to control the internal cyw43570 regu lators. when this pin is high, the regulators are enabled and the wlan section is out of reset. when this pin is low, the wlan section is in reset. if bt_reg_on and wl_reg_on are both low, the regulators are disabled. this pin has an internal 200 kw pull-down resistor that is enabled by default. it can be disabled through programming. bt_reg_on this signal is used by the pmu (with wl_r eg_on) to decide whether or not to power down the internal cyw43570 regulators. if bt_reg_on and wl_reg_on are low, the regulators will be disabled. this pin has an internal 200 kw pull-down resistor that is enabled by default. it can be disabled through programming.
document number: 002-15054 rev. *i page 13 of 94 advance cyw43570 3. frequency references an external crystal is used for generating all radio frequencies and normal operation clocking. as an alternative, an external frequency reference may be used. in addition, a low-power oscillator (lpo) is provided for lower power mode timing. 3.1 crystal interface and clock generation the cyw43570 can use an external crystal to provide a frequency reference. the recommended configuration for the crystal oscill ator including all external components is shown in figure 4 . consult the reference schematics for the latest configuration. figure 4. recommended oscillator configuration a fractional-n synthesizer in the cyw435 70 generates the radio frequencies, clocks, and data/packet timing, enabling it to oper ate using a wide selection of frequency references. the recommended default frequency reference is a 40.0 mhz crystal. the signal characteristics for the crystal interface are lis ted in ta b l e 4 . note: although the fractional-n synthesizer can support alternative re ference frequencies, frequencies other than the default require support to be added in the driver, plus additional ext ensive system testing. contact cypress for further details. wrf_xtal_out wrf_xtal_in c* c* x ? ohms* *values ? determined ? by ? crystal ? drive ? level. ? see ? reference ? schematics ? for ? details. ? 40.0 ? mhz
document number: 002-15054 rev. *i page 14 of 94 advance cyw43570 3.2 external frequency reference table 4. crystal oscillator and external clock?requirements and performance parameter conditions/notes crystal a a. (crystal) use wrf_xtal_in and wrf_xtal_out. external frequency reference b c b. see 3.2 external frequency reference for alternative connection methods. c. for a clock reference other than 40 mhz, 20 log10(f/40) db s hould be added to the limits, where f = the reference clock fre quency in mhz. min typ max min typ max units frequency 2.4g and 5g bands: ieee 802.11ac operation ?40????mhz frequency tolerance over the lifetime of the e quipment, including temperature d d. it is the responsibility of the equipment designer to select oscillator components that comply with these specifications. without trimming ?20 ? 20 ?20 ? 20 ppm crystal load capacitance ? ? 12 ????pf esr ? ? ? 60 ? ? ? ? drive level external cryst al must be able to tolerate this drive level. 200????? w input impedance (wrf_xtal_in) resistive ? ? ? 30 100 ? k ? capacitive ? ? 7.5 ? ? 7.5 pf wrf_xtal_in input low level dc-coupled digital signal ???0?0.2v wrf_xtal_in input high level dc-coupled digital signal ? ? ? 1.0 ? 1.26 v wrf_xtal_in input voltage ac-coupled analog signal ? ? ? 400 ? 1200 mv p-p duty cycle 40 mhz clock ? ? ? 40 50 60 % phase noise e (ieee 802.11b/g) e. assumes that the external clock has a flat phase noise response above 100 khz. 40 mhz clock at 10 khz offset ??????129dbc/ hz 40 mhz clock at 100 khz offset??????136dbc/ hz phase noise e (ieee 802.11a) 40 mhz clock at 10 khz offset ??????137dbc/ hz 40 mhz clock at 100 khz offset??????144dbc/ hz phase noise e (ieee 802.11n, 2.4 ghz) 40 mhz clock at 10 khz offset ??????134dbc/ hz 40 mhz clock at 100 khz offset??????141dbc/ hz phase noise e (ieee 802.11n, 5 ghz) 40 mhz clock at 10 khz offset ??????142dbc/ hz 40 mhz clock at 100 khz offset??????149dbc/ hz phase noise e (ieee 802.11ac, 5 ghz) 40 mhz clock at 10 khz offset ??????150dbc/ hz 40 mhz clock at 100 khz offset??????157dbc/ hz
document number: 002-15054 rev. *i page 15 of 94 advance cyw43570 4. bluetooth overview the cyw43570 is a bluetooth 4.1 + edr-comp liant, baseband processor/2.4 ghz transceiv er. it features the highest level of integration and eliminates all critical exte rnal components, thus minimizing the foot print, power consumption, and system cost of a bluetooth radio solution. the cyw43570 is the op timal solution for any bl uetooth voice and /or data application. the bluetooth subsyst em presents a standa rd host controller interface (hci) via a high-speed uart and pcm for audio. the cyw43570 incorporates all bluetooth 4.1 + edr features including secure simple pairing, sn iff subrating, and encryption pause and resume. the cyw43570 bluetooth radio transceiver provides enhanced radio performance to meet the most stringent mobile phone temperature applications and the tightest integration into mobile handsets and portable devices. it is fully compatible with an y of the standard tcxo frequencies and provides full radio compatibility to operate simultaneously with gps, wlan, and cellular radios. the bluetooth transmitter also features a cla ss 1 power amplifier with class 2 capability. 4.1 features major bluetooth features of the cyw43570 include: supports key features of upcoming bluetooth standards fully supports bluetooth core specif ication version 4.1 + edr features: ? adaptive frequency hopping (afh) ? quality of service (qos) ? extended synchronous connections (esco)?voice connections ? fast connect (interlaced page and inquiry scans) ? secure simple pairing (ssp) ? sniff subrating (ssr) ? encryption pause resume (epr) ? extended inquiry response (eir) ? link supervision timeout (lst) uart baud rates up to 4 mbps supports all bluetooth 4.1 + edr packet types maximum bluetooth data rates over hci uart (interface c apable but not currently supported in the software driver) bt supports full-speed usb 2.0-compliant interface multipoint operation with up to seven active slaves ? maximum of seven simultaneous active acl links ? maximum of three simultaneous active sco and esco connections with scatternet support trigger broadcom fast connect (tbfc) narrowband and wideband packet loss concealment scatternet operation with up to four active pic onets with background scan and support for scatter mode high-speed hci uart transport support with low-power out-of-band bt_dev_wake and bt_host_wake signaling (see host controller power management ) channel quality driven data rate and packet type selection standard bluetooth test modes extended radio and produc tion test mode features
document number: 002-15054 rev. *i page 16 of 94 advance cyw43570 full support for power savings modes ? bluetooth clock request ? bluetooth standard sniff ? deep-sleep modes and software regulator shutdown tcxo input and auto-detection of all standard handset clock fre quencies. also supports a low-power crystal, which can be used during power save mode for better timing accuracy. improved audio interface capabilities with full-featured bidirectional pcm and i 2 s i 2 s can be master or slave 4.2 bluetooth radio the cyw43570 has an integrated radio transce iver that has been optimized for use in 2.4 ghz bluetoot h wireless systems. it has been designed to provide low-power, low-cost, robust communicati ons for applications operating in the globally available 2.4 gh z unlicensed ism band. it is fully compliant with the bluetooth radio specification and edr specification and meets or exceeds th e requirements to provide the highest communication link quality of service. an integrated t/r swit ch combines bluetooth transmit and receive paths, and connects directly to a dedicated bluetooth antenna. 4.2.1 transmit the cyw43570 features a fully integrated ze ro-if transmitter. the baseband transmit da ta is gfsk-modulated in the modem block and upconverted to the 2.4 ghz ism band in the transmitter path. the transmitter path consists of signal filtering, i/q upconve rsion, output power amplifier, and rf filtering. the transmitter path also incorporates ? /4-dqpsk for 2 mbps and 8-dpsk for 3 mbps to support edr. the transmitter section is compatible to the bluetoot h low energy specification. the transmitter pa bias can also be adjusted to provide bluetooth class 1 or class 2 operation. 4.2.2 digital modulator the digital modulator performs the data modu lation and filtering required for the gfsk, ? /4-dqpsk, and 8-dpsk signal. the fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the trans- mitted signal and is much more stable than direct vco modulation schemes. 4.2.3 digital demodulator and bit synchronizer the digital demodulator and bit synchronizer take the low-if received signal and perform an optimal frequency tracking and bit- synchronization algorithm. 4.2.4 power amplifier the fully integrated pa supports class 1 or class 2 output using a highly linearized, temperature-compensated design. this prov ides greater flexibility in front-end matching and filtering. due to th e linear nature of the pa combi ned with some integrated filte ring, external filtering is required to meet the bluetooth and regulatory harmonic and spurious requirements. for integrated mobile handset ap pli- cations in which bluetooth is integrated next to the cellular radio, external filtering can be applied to achieve near thermal noise levels for spurious and radiated noise emissions. the transmitter featur es a sophisticated on-chip transm it signal strength indicator (tssi) block to keep the absolute output power variation withi n a tight range across process, voltage, and temperature. 4.2.5 receiver the receiver path uses a low-if scheme to downconvert the rece ived signal for demodulation in the digital demodulator and bit synchronizer. the receiver path provides a high degree of linear ity, an extended dynamic range, and high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 ghz ism band. the front-end topology wi th built-in out-of-band attenuat ion enables the cyw43570 to be used in most appl ications with minimal off-chip filtering. for integrated handset operation, in whic h the bluetooth function is integrated close to the cellular transmitter, external filtering is requir ed to eliminate the desensitiza tion of the receiver by the cellular transmit signal.
document number: 002-15054 rev. *i page 17 of 94 advance cyw43570 4.2.6 digital demodulator and bit synchronizer the digital demodulator and bit synchronizer take the low-if received signal and perform an optimal frequency tracking and bit synchronization algorithm. 4.2.7 receiver signal strength indicator the radio portion of the cyw43570 provides a receiver signal strength indicator (rssi) signal to the baseband, so that the cont roller can take part in a bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine wheth er the transmitter should increase or decrease its output power. 4.2.8 local oscillator generation a local oscillator (lo) generation provides fast frequency hoppi ng (1600 hops/second) across the 79 maximum available channels. the lo generation subblock employs an architecture for high immu nity to lo pulling during pa operation. the cyw43570 uses an internal rf and if loop filter. 4.2.9 calibration the cyw43570 radio transceiver features an automated calibration sch eme that is fully self contained in the radio. no user inte raction is required during normal operation or during manufacturing to provide the optimal performance. calibration optimizes the perfo r- mance of all the major blocks within the radio to within 2% of optimal conditions, including gain and phase characteristics of filters, matching between key components, and key gain blocks. this take s into account process variation and temperature variation. calibration occurs transparently during normal operation during t he settling time of the hops and calibrates for temperature va riations as the device cools and heats during normal operation in its environment.
document number: 002-15054 rev. *i page 18 of 94 advance cyw43570 5. bluetooth baseband core the bluetooth baseband core (bbc) im plements all of the time critic al functions required for high- performance bluetooth operati on. the bbc manages the buffering, segmentation, and routing of dat a for all connections. it also buffers data that passes through it, handles data flow control, schedul es sco/acl tx/rx transactions, monitors blueto oth slot usage, optimal ly segments and packages data into baseband packets, manages connection status indicators , and composes and decodes hci packets. in addition to these functions, it independently handles hci event types, and hci command types. the following transmit and receive functions are also implemented in the bbc hardware to increase reliability and security of t he tx/ rx data before sending over the air: symbol timing recovery, data deframing, forward error correct ion (fec), header error control (hec), cyclic redundancy check (crc), data decryption, and data dewhitening in the receiver. data framing, fec generation, hec generat ion, crc generation, key generation, data encryption, and data whitening in the transmitter. 5.1 bluetooth 4.1 features the bbc supports all bluetooth 4.1 features with the following benefits: dual-mode bluetooth low energy (bt and ble operation) extended inquiry response (eir): shortens the time to retr ieve the device name, specif ic profile, and operating mode. encryption pause resume (epr): enables the use of bluet ooth technology in a much more secure environment. sniff subrating (ssr): optimizes power consumption for low duty cycle asymmetric data flow, wh ich subsequently extends battery life. secure simple pairing (ssp): reduces the num ber of steps for conn ecting two devices, wi th minimal or no us er interaction requir ed. link supervision time out (lsto): additional commands added to hci and link management protocol (lmp) for improved link time- out supervision. qos enhancements: changes to data traffic control, which result s in better link performance. audio, human interface device (hid ), bulk traffic, sco, and enhanced sco (esco) are improved with the erroneous data (ed) and packet boundary flag (pbf) enhance- ments. 5.2 bluetooth low energy the cyw43570 supports the bluetooth low energy operating mode. 5.3 link control layer the link control layer is part of the bluetooth link control func tions that are implemented in dedicated logic in the link cont rol unit (lcu). this layer consists of the command contro ller that takes commands from the software, and other controllers that are activated o r configured by the command cont roller, to perform the link cont rol tasks. each task pe rforms a different state in the bluetooth link controller. major states: ? standby ? connection substates: ? page ? page scan ? inquiry ? inquiry scan ? sniff
document number: 002-15054 rev. *i page 19 of 94 advance cyw43570 5.4 test mode support the cyw43570 fully supports bluetooth test mode as described in part i:1 of the specif ication of the bluetooth system version 3. 0. this includes the transmitter tests, normal and del ayed loopback tests, and reduced hopping sequence. in addition to the standard bluetooth test mode, the cyw43570 also supports enhanced testing features to simplify rf debugging and qualification and type-approval testing. these features include: fixed frequency carrier wave (unmodulated) transmission ? simplifies some type-approval measurements (japan) ? aids in transmitter performance analysis fixed frequency constant receiver mode ? receiver output directed to i/o pin ? allows for direct ber measurements using standard rf test equipment ? facilitates spurious emissions testing for receive mode fixed frequency constant transmission ? eight-bit fixed pattern or prbs-9 ? enables modulated signal measurements with standard rf test equipment 5.5 bluetooth power management unit the bluetooth power management unit (pmu) pr ovides power management featur es that can be invoked by either software through power management registers or packet handling in the baseband co re. the power management functions provided by the cyw43570 are: rf power management host controller power management bbc power management 5.5.1 rf power management the bbc generates power-down control signals for the transmit path, receive path, pll, and power amplifier to the 2.4 ghz trans - ceiver. the transceiver then processes the power-down functions accordingly. 5.5.2 host controller power management when running in uart mode, the cyw43570 can be configured so that dedicated signals ar e used for power management hand- shaking between it and the host. the basic power-saving functions supported by those hand-shakin g signals include the standard bluetooth defined power savings modes and standby modes of operation. ta b l e 5 describes the power-control hand-shak e signals used with the uart interface. table 5. power control pin description signal mapped to pin type description bt_dev_wake j1 i bluetooth device wake-up: signal from the host to the cyw43570 indicating that the host requires attention. asserted: the bluetooth device must wake-up or remain awake. deasserted: the bluetooth device may sleep when sleep criteria are met. the polarity of this signal is software configurable and can be asserted high or low. bt_host_wake j2 o host wake up. signal from the cyw43570 to the host indicating that the cyw43570 requires attention. asserted: host devi ce must wake-up or remain awake. deasserted: host device may sleep when sleep criteria are met. the polarity of this signal is software configurable and can be asserted high or low. this is an active-low signal that require external pull-up resistor 10k for operation. bt_clk_req j5 o the cyw43570 asserts bt_clk _req when bluetooth or wlan wants the host to turn on the reference clock. t he bt_clk_req polarity is active-high. add an external 100 k ? pull-down resistor to ensure the signal is deasserted when the cyw43570 powers up or resets when vddio is present. note: pad function control register is set to 0 for these pins (see section 13. dc characteristics ).
document number: 002-15054 rev. *i page 20 of 94 advance cyw43570 figure 5. startup signaling sequence hostresetx vddio lpo bt_dev_wake bt_uart_rts_l bt_clk_req bt_host_wake bt_reg_on bt_uart_cts_l host ? ios ? configured host ? i/os ? unconfigured bt ? i/os ? configured bt ? i/os ? unconfigured t 3 t settle t settle t 2 t 4 t 1 notes ? : ?? ? t 1 is ? the ? time ? for ? host ? to ? settle ? its ? ios ? after ? a ? reset. ? t 2 is ? the ? time ? for ? the ? bth ? device ? to ? settle ? its ? ios ? after ? a ? reset ? and ? reference ? clockk ? settling ? time ? elapsed. ? t 3 is ? the ? time ? for ? the ? bt ? device ? to ? complete ? initialization ? and ? drive ? bt_uart_rts_l ? low. ? t 4 is ? the ? setup ? time ? for ? bt_dev_wake ? prior ? to ? driving ? bt_reg_on ? high; ? bt_dev_wake ? must ? be ? high ? prior ? to ? bt_reg_on ? being ? released. ? bt_dev_wake ? should ? not ? be ? driven ? low ? until ? after ? the ? host ? has ? completed ? configuration. ? t settle is ? the ? time ? for ? the ? reference ? clock ? signal ? from ? the ? host ? to ? be ? guaranteed ? to ? have ? settled. driven pulled indicates ? that ? the ? bt ? device ? is ? ready
document number: 002-15054 rev. *i page 21 of 94 advance cyw43570 5.5.3 bbc power management the following are low-power operations for the bbc: physical layer packet-handling turns the rf on and off dynamically within transmit/receive packets. bluetooth-specified low-power connection m odes: sniff, hold, and park. while in these modes, the cyw43570 runs on the low- power oscillator and wakes up after a predefined time period. a low-power shutdown feature allows the device to be turned off while the host and any other devices in the system remain operational. when the cyw43570 is not needed in the system, the rf and core supplies are shut down while the i/o remains powered. this allows the cyw43570 to effectively be off while keeping the i/o pins powered so they do not draw extra current from any other devices connected to the i/o. during the low-power shut-down state, provided vddio remains a pplied to the cyw43570, all outpu ts are tristated, and most input signals are disabled. input voltages mu st remain within the limits defined for no rmal operation. this is done to prevent current paths or create loading on any digital signals in the system and enables the cyw43570 to be fully integrated in an embedded device to take full advantage of the lowest power-saving modes. two cyw43570 input signals are designed to be high-impedance inputs that do not load the driving si gnal even if the chip does not have vddio power supplied to it: the frequency reference i nput (wrf_tcxo_in) and the 32.768 khz input (lpo). when the cyw43570 is powered on from this state, it is the same as a normal power-up, and the device does not contain any information about its state from the time before it was powered down. 5.5.4 wideband speech the cyw43570 provides support for wideband speech (wbs) us ing on-chip smartaudio technology. the cyw43570 can perform subband codec (sbc), as well as msbc, en coding, and decoding of linear 16 bits at 16 khz (256 kbps rate) transferred over the pc m bus. 5.5.5 packet loss concealment packet loss concealment (plc) improves apparent audio quality for systems with marginal link per formance. bluetooth messages are sent in packets. when a packet is lost, it creates a gap in the received audio bit-stream. packet loss can be mitigated in several ways: fill in zeros. ramp down the output audio signal toward zero (this is the method used in current bluetooth headsets). repeat the last frame (or packet) of the received bi t-stream and decode it as usual (frame repeat). these techniques cause distortion and popping in the audio stre am. the cyw43570 uses a proprietary waveform extension algorithm to provide dramatic improvem ent in the audio quality. figure 6 and figure 7 show audio waveforms with and without packet loss concealment. cypress plc/bec algori thms also support wideband speech. figure 6. cvsd decoder output waveform without plc packet loss causes ramp-down
document number: 002-15054 rev. *i page 22 of 94 advance cyw43570 figure 7. cvsd decoder output waveform after applying plc 5.5.6 audio rate-matching algorithms the cyw43570 has an enhanced rate-matching algorithm that uses in terpolation algorithms to reduc e audio stream jitter that may be present when the rate of audio data coming from the host is not the same as t he bluetooth audio data rates. 5.5.7 codec encoding the cyw43570 can support sbc and msbc encoding and decoding for wideband speech. 5.5.8 multiple simult aneous a2dp audio stream the cyw43570 has the ability to take a single audio stream and ou tput it to multiple bluetooth devices simultaneously. this all ows a user to share his or her music (or any audio stream) with a friend. 5.5.9 burst buffer operation the cyw43570 has a data buffer that can buff er data being sent over the hci and audi o transports, then send the data at an incr eased rate. this mode of operat ion allows the host to sleep for the maximum amo unt of time, dramatically reducing system current consumption. 5.6 adaptive frequency hopping the cyw43570 gathers link quality statistics on a channel by channel basis to facilitate channel assessment and channel map selection. the link quality is determined using both rf and base band signal processing to provide a more accurate frequency-hop map. 5.7 advanced bluetooth/wlan coexistence the cyw43570 includes advanced coexistence technologies that are only possible with a bluetooth/wlan integrated die solution. these coexistence technologies are targeted at small form-factor platforms, such as sm art tvs, over-the-top (ott) boxes, set-to p boxes, and wireless speakers, including applications such as vowlan + sco and video-over-wlan + high-fidelity bt stereo. the cyw43570 integrated solution enables mac-layer signaling (fi rmware) and a greater degree of sharing via an enhanced coexis- tence interface. information is exchanged between the blue tooth and wlan cores without host processor involvement. the cyw43570 also supports transmit power control on the sta to gether with standard blue tooth tpc to limit mutual interference and receiver desensitization. pr eemption mechanisms are utilized to prevent ap transmissions from colliding with bluetooth fram es. improved channel classification techniques have been implemented in bluetooth for faster and more accurate detection and elimi- nation of interferers (including non-wlan 2.4 ghz interference). the bluetooth afh classification is also enhanced by the wlan core?s channel information. 5.8 fast connection (interlaced page and inquiry scans) the cyw43570 supports page scan and inquiry scan modes that sign ificantly reduce the average inquiry response and connection times. these scanning modes are compatible with the bluetooth version 2.1 page and inquiry procedures.
document number: 002-15054 rev. *i page 23 of 94 advance cyw43570 6. microprocessor and memory unit for bluetooth the bluetooth microprocessor core is based on the arm cortex -m3 32-bit risc processor with embedded ice-rt debug and jtag interface units. it runs software fr om the link control (lc) layer, up to the host controller interface (hci). the arm core is paired with a memory unit that contains 668 kb of rom memory for program stor age and boot rom, 200 kb of ram for data scratchpad and patch ram code. the internal rom a llows for flexibility during power-on reset to enable the same de vice to be used in various configurations. at power-up, the lower-lay er protocol stack is executed from the internal rom memory. external patches may be applied to the rom-based firmware to pr ovide flexibility for bug fixes or features additions. these pat ches may be downloaded from the host to the cyw43570 through the uart transports. 6.1 ram, rom, and patch memory the cyw43570 bluetooth core has 200 kb of internal ram whic h is mapped between general purpose scratch pad memory and patch memory and 668 kb of rom used for t he lower-layer protocol stack, test mode software, and boot rom. the patch memory capability enables the addition of code changes for purpose s of feature additions and bug fixes to the rom memory. 6.2 reset the cyw43570 has an integrated power-on reset circuit that resets all circuits to a known power-on state. the bt power-on reset (por) circuit is out of reset after bt_reg_on goes high. if bt_reg_on is low, then the por circuit is held in reset.
document number: 002-15054 rev. *i page 24 of 94 advance cyw43570 7. bluetooth periph eral transport unit 7.1 spi/uart transport detection the bt_host_wake pin is also used for bt transport detection. the transport detection occurs during the power-up sequence. it selects either uart or spi transport op eration based on the following pin states: if the bt_host_wake pin is pulled low by an external pull-down during power-up, it selects the spi transport interface. if the bt_host_wake pin is not pulled low externally during powe r-up, then the default internal pull-up is detected as a high a nd it selects the uart transport interface. 7.2 pcm interface the cyw43570 supports two independent pcm interfaces t hat share pins with the serial flash interfaces. ta b l e 6 shows pcm signal mapping used in this data sheet: the pcm interface on the cyw43570 can connect to linear pcm co dec devices in master or slav e mode. in master mode, the cyw43570 generates the bt_pcm_clk and bt_pcm_sync signals, and in slave mode, these signals are provided by another master on the pcm interface a nd are inputs to the cyw43570. the configuration of the pcm interface may be adjusted by the host through the use of vendor-specific hci commands. 7.2.1 slot mapping the cyw43570 supports up to three simultaneous full-duplex sco or esco channels through the pcm interface. these three channels are time-multiplexed onto the single pcm interface by us ing a time-slotting scheme where the 8 khz or 16 khz audio sam ple interval is divided into as many as 16 slots. the number of slots is dependent on the selected in terface rate of 128 khz, 512 k hz, or 1024 khz. the corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. transmit and receive pcm data from an sco channel is always mapped to the same slot. t he pcm data output driver tristate s its output on unused slots to allow other devices to share the same pcm interface signals. the data output driver tristates its ou tput after the falling edge of th e pcm clock during the last bit of the slot. 7.2.2 frame synchronization the cyw43570 supports both short- and long- frame synchronization in both master and slave modes. in short-frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. the pcm slave looks for a high on the falling edge of the bit clock and expec ts the first bit of the first slot to start at th e next rising edge of the cl ock. in long-frame synchroni zation mode, the frame synchr onization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts c oincident with the first bit of the first slot. 7.2.3 data formatting the cyw43570 may be configured to generat e and accept several different data formats. for conventional narrow band speech mode, the cyw43570 uses 13 of the 16 bits in each pcm frame. t he location and order of these 13 bits can be configured to suppo rt various data formats on the pcm interface. the remaining three bi ts are ignored on the input and may be filled with 0s, 1s, a s ign bit, or a programmed value on the output. the default format is 13-bi t 2?s complement data, left ju stified, and clocked msb first. table 6. pcm-to-serial flash interface mapping pcm interface pins serial flash interface pins bt_pcm_clk bt_sf_clk bt_pcm_in bt_sf_miso bt_pcm_out bt_sf_mosi bt_pcm_sync bt_sf_cs_l
document number: 002-15054 rev. *i page 25 of 94 advance cyw43570 7.2.4 wideband speech support when the host encodes wideband speech (wbs) packets in tran sparent mode, the encoded packet s are transferred over the pcm bus for an esco voice connection. in this mode, the pcm bus is ty pically configured in master m ode for a 4 khz sync rate with 1 6- bit samples, resulting in a 64 kbps bit rate. the cyw43570 also supports slave transparent mode using a proprietary rate-matchi ng scheme. in sbc-code mode, linear 16-bit data at 16 kh z (256 kbps rate) is transferred over the pcm bus. 7.2.5 burst pcm mode in this mode of operation, the pcm bus runs at a significantly higher rate of operati on to allow the host to duty cycle its ope ration and save current. in this mode of operation, the pcm bus can operate at a rate of up to 24 mhz. this mode of operation is initiated with an hci command from the host. 7.2.6 pcm interface timing short frame sync, master mode figure 8. pcm timing diagram (short frame sync, master mode) table 7. pcm interface timing specifications (short frame sync, master mode) reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4bt_pcm_sync delay 0?25ns 5 bt_pcm_out delay 0 ? 25 ns 6 bt_pcm_in setup 8 ? ? ns 7 bt_pcm_in hold 8??ns 8 delay from rising edge of bt_pcm_bclk during last bit period to bt_pcm_out becoming high impedance. 0?25ns bt_pcm_clk bt_pcm_sync bt_pcm_out 1 23 4 5 bt_pcm_in 6 8 high ? impedance 7
document number: 002-15054 rev. *i page 26 of 94 advance cyw43570 short frame sync, slave mode figure 9. pcm timing diagram (short frame sync, slave mode) table 8. pcm interface timing specifications (short frame sync, slave mode) reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 bt_pcm_sync setup 8??ns 5 bt_pcm_sync hold 8??ns 6 bt_pcm_out delay 0?25ns 7 bt_pcm_in setup 8??ns 8 bt_pcm_in hold 8??ns 9 delay from rising edge of bt_pcm_clk during last bit period to bt_pcm_out becoming high impedance. 0?25ns bt_pcm_clk bt_pcm_sync bt_pcm_out 1 23 4 5 6 bt_pcm_in 7 9 high ? impedance 8
document number: 002-15054 rev. *i page 27 of 94 advance cyw43570 long frame sync, master mode figure 10. pcm timing diagram (long frame sync, master mode) table 9. pcm interface timing specifications (long frame sync, master mode) reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 bt_pcm_sync delay 0 ? 25 ns 5bt_pcm_out delay 0?25ns 6 bt_pcm_in setup 8 ? ? ns 7 bt_pcm_in hold 8 ? ? ns 8 delay from rising edge of bt_pcm_clk during last bit period to bt_pcm_out becoming high impedance. 0?25ns bt_pcm_clk bt_pcm_sync bt_pcm_out 1 23 4 5 bt_pcm_in 8 high ? impedance bit ? 0 bit ? 0 bit ? 1 bit ? 1 6 7
document number: 002-15054 rev. *i page 28 of 94 advance cyw43570 long frame sync, slave mode figure 11. pcm timing diagram (long frame sync, slave mode) table 10. pcm interface timing specifications (long frame sync, slave mode) reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 bt_pcm_sync setup 8 ? ? ns 5 bt_pcm_sync hold 8??ns 6 bt_pcm_out delay 0 ? 25 ns 7 bt_pcm_in setup 8 ? ? ns 8 bt_pcm_in hold 8??ns 9 delay from rising edge of bt_pcm_clk during last bit period to bt_pcm_out becoming high impedance. 0?25ns bt_pcm_clk bt_pcm_sync bt_pcm_out 1 23 4 5 6 bt_pcm_in 7 9 high ? impedance 8 bit ? 0 bit ? 0 bit ? 1 bit ? 1
document number: 002-15054 rev. *i page 29 of 94 advance cyw43570 short frame sync, burst mode figure 12. pcm burst mode timing (receive only, short frame sync) table 11. pcm burst mode (rece ive only, short frame sync) reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 24 mhz 2 pcm bit clock low 20.8 ? ? ns 3 pcm bit clock high 20.8 ? ? ns 4 bt_pcm_sync setup 8 ? ? ns 5 bt_pcm_sync hold 8 ? ? ns 6 bt_pcm_in setup 8 ? ? ns 7 bt_pcm_in hold 8??ns bt_pcm_clk bt_pcm_sync 1 23 45 bt_pcm_in 6 7
document number: 002-15054 rev. *i page 30 of 94 advance cyw43570 long frame sync, burst mode figure 13. pcm burst mode timing (receive only, long frame sync) table 12. pcm burst mode (receive only, long frame sync) reference characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 24 mhz 2 pcm bit clock low 20.8 ? ? ns 3 pcm bit clock high 20.8 ? ? ns 4 bt_pcm_sync setup 8??ns 5 bt_pcm_sync hold 8??ns 6 bt_pcm_in setup 8??ns 7 bt_pcm_in hold 8??ns bt_pcm_clk bt_pcm_sync 1 2 3 4 5 bt_pcm_in 6 7 bit ? 0 bit ? 1
document number: 002-15054 rev. *i page 31 of 94 advance cyw43570 7.3 usb interface 7.3.1 features the following usb interface features are supported: usb protocol, revision 2.0, full-speed (12 mbps) compliant including the hub optional hub compound device with up to three device cores internal to device bus or self-power, dynamic configuration for the hub global and selective suspend and resume with remote wakeup bluetooth hci hid and dfu integrated detach resistor 7.3.2 operation the cyw43570 can be configured to boot up as either a single u sb peripheral or a usb hub with several usb peripherals attached. as a single peripheral, the host detects a single usb bluetooth dev ice. in hub mode, the host detects a hub with one to three o f the ports already connected to usb devices (see figure 14 ). figure 14. usb compounded device configuration depending on the desired hub mode configuration, the cyw43570 can boot up showing the three ports connected to logical usb devices internal to the cyw43570: a generic bluetooth device, a mouse, and a keyboard. in this mode, the mouse and keyboard are emulated devices, since they connect to real hid devices via a bl uetooth link. the bluetooth link to these hid devices is hidde n from the usb host. to the host, the mouse and/or keyboard appear to be directly connected to the usb port. the usb device, configuration, and string descriptors are fully programmable, allowing manufacturers to customize the descripto rs, including vendor and product ids, the cyw43570 uses to identify itself on the usb port. to make custom usb descriptor informati on available at boot time, stor ed it in external nvram. despite the mode of operation (single peripher al or hub), the bluetooth device is conf igured to include the following interface s: interface 0 contains a control endpoint (endpoint 0x00) for hci commands, a bulk in endpoint (endpoint 0x82) for receiving acl data, a bulk out endpoint (endpoint 0x02) for transmitting acl data, and an interrupt endpoint (endpoint 0x81) for hci events. interface 1 contains isochronous in and ou t endpoints (endpoints 0x83 and 0x03) for sco traffic. several alternate interface 1 settings are available for re serving the proper bandwidth of isochronous data (depending on the application). interface 2 contains bulk in and bulk out endpoints (endpoint s 0x84 and 0x04) used for proprietary testing and debugging purposes. these endpoints can be ignored during normal operation. usb ? compounded ? device hub ? controller usb ? device ? 1 hid ? keyboard ? usb ? device ? 2 hid ? mouse usb ? device ? 3 bluetooth host
document number: 002-15054 rev. *i page 32 of 94 advance cyw43570 the cyw43570 supports the usb hub and device model (usb, revision 2.0, full-speed compliant). when the hub is enabled, the cyw43570 handles all standard usb functions for the following devices: hid keyboard hid mouse bluetooth all hub and device descriptors are firmware-programmab le. this usb compound device configuration (see figure 14 ) supports up to three downstream ports. this configuration can also be programm ed to a single usb device core. the device automatically detects activity on the usb interface when connec ted. therefore, no s pecial configuration is needed to select hci as the transport. the hub?s downstream port definition is as follows: port 1 usb lite device core (for hid applications) port 2 usb lite device core (for hid applications) port 3 usb full device core (for bluetooth applications) when operating in hub mode, all three internal devices do not ha ve to be enabled. each internal usb device can be optionally en abled. the configuration record in nvram de termines which devices are present. 7.3.3 usb full-speed timing ta b l e 1 3 shows timing specifications for the vdd_usb = 3.3v, v ss = 0v, and t a = 0c to 85c operating temperature range. figure 15. usb full-speed timing 7.4 uart interface the cyw43570 has a uart host interface for bluetooth. the uart is a standard 4-wire interface (rx, tx, rts, and cts) with adjustable baud rates from 9600 bps to 4.0 mbps. the interface features an automatic baud rate detection capability that return s a baud rate selection. alternatively, the baud rate may be selected through a vendor-specific uart hci command. the uart has a 1040-byte receive fifo and a 1040-byte transmit fifo to support edr. access to the fifos is conducted through the ahb interface through either dma or th e cpu. the uart supports the bluetooth 4. 1 uart hci specification: h4, a custom extended h4, and h5. the default baud rate is 115.2 kbaud. the uart supports the 3-wire h5 uart transport, as described in the bluetooth specification ( three-wire uart transport layer ). compared to h4, the h5 uart transport reduces the number of signal lines required by eliminating the cts and rts signals. the cyw43570 uart can perform xon/xoff flow control and includes hardware support for the serial line input protocol (slip). it can also perform wake-on activi ty. for example, activity on the rx or cts inputs can wake the chip from a sleep state. table 13. usb full-speed timing specifications reference characteristics minimum maximum unit 1 transition rise time 4 20 ns 2 transition fall time 4 20 ns 3 rise/fall timing matching 90 111 % 4 full-speed data rate 12 ? 0.25% 12 + 0.25% mbps d+ d- v crs 90% 90% 10% 10% 1 2
document number: 002-15054 rev. *i page 33 of 94 advance cyw43570 normally, the uart baud rate is set by a configuration record downloaded after device reset, or by automatic baud rate detectio n, and the host does not need to adjust the baud rate. support for changing the baud rate during normal hci uart operation is incl uded through a vendor-specific command that allo ws the host to adjust the contents of t he baud rate registers. the cyw43570 uarts operate correctly with the host uart as long as the co mbined baud rate error of the two devices is within 2%. figure 16. uart timing table 14. example of common baud rates desired rate actual rate error (%) 4000000 4000000 0.00 3692000 3692308 0.01 3000000 3000000 0.00 2000000 2000000 0.00 1500000 1500000 0.00 1444444 1454544 0.70 921600 923077 0.16 460800 461538 0.16 230400 230796 0.17 115200 115385 0.16 57600 57692 0.16 38400 38400 0.00 28800 28846 0.16 19200 19200 0.00 14400 14423 0.16 9600 9600 0.00 table 15. uart timi ng specifications reference characteristics minimum typical maximum unit 1 delay time, bt_uart_cts_l low to bt_uart_txd valid ? ? 1.5 bit periods 2 setup time, bt_uart_cts_l hi gh before midpoint of stop bit ? ? 0.5 bit periods 3 delay time, midpoint of stop bit to bt_uart_rts_l high ? ? 0.5 bit periods bt_uart_cts_l bt_uart_rxd 1 2 midpoint ? of ? stop ? bit bt_uart_txd midpoint ? of ? stop ? bit 3 bt_uart_rts_l
document number: 002-15054 rev. *i page 34 of 94 advance cyw43570 7.5 i 2 s interface the cyw43570 supports an i 2 s digital audio port for bluetooth audio. the i 2 s interface supports both master and slave modes. the i 2 s signals are: i 2 s clock: bt_i2s_clk i 2 s word select: bt_i2s_ws i 2 s data out: bt_i2s_do i 2 s data in: bt_i2s_di bt_i2s_clk and bt_i2s_ws become outputs in master mode and inputs in slave mode, whereas bt_i2s_do always stays as an output. the channel word length is 16 bits, and the data is just ified so that the msb of the le ft-channel data is aligned with the msb of the i 2 s bus, in accord with the i 2 s specification. the msb of each data word is transmitted one bit clock cycle af ter the bt_i2s_ws transition, synchronous with the falling edge of the bit clock. left-channel data is transmitted when ibt_i2s_ws is low, and ri ght- channel data is transmitted when bt_i2s_ws is high. data bits sent by the cyw43570 are synchronized with the falling edge of bt_i2s_clk and should be sampled by the re ceiver on the rising edge of bt_i2s_clk. the clock rate in master mode is either of the following: 48 khz x 32 bits per frame = 1.536 mhz 48 khz x 50 bits per frame = 2.400 mhz the master clock is generated from the inpu t reference clock using a n/m clock divider. in the slave mode, any clock rate is supported to a maximum of 3.072 mhz.
document number: 002-15054 rev. *i page 35 of 94 advance cyw43570 7.5.1 i 2 s timing note: timing values specified in table 16 are relative to high and low threshold levels. table 16. timing for i 2 s transmitters and receivers transmitter receiver notes lower limit upper limit lower limit upper limit min max min max min max min max clock period t t tr ???t r ??? a a. the system clock period t must be greater than t tr and t r because both the transmitter and receiver have to be able to handle the data transfer rate. master mode: clock generated by transmitter or receiver high t hc 0.35t tr ???0.35t tr ??? b b. at all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. for thi s reason, t hc and t lc are specified with respect to t. lowt lc 0.35t tr ???0.35t tr ??? b slave mode: clock accepted by transmitter or receiver high t hc ?0.35t tr ? ? ? 0.35t tr ?? c c. in slave mode, the transmitter and receiver need a clock signal wi th minimum high and low periods so that they can detect the signal. so long as the minimum periods are greater than 0.35t r , any clock that meets the requirements can be used. low t lc ?0.35t tr ? ? ? 0.35t tr ?? c rise time t rc ? ? 0.15t tr ????? d d. because the delay (t dtr ) and the maximum transmitter speed (defined by t tr ) are related, a fast transmitte r driven by a slow clock edge can result in t dtr not exceeding t rc which means t htr becomes zero or negative. therefore, the transmitter has to guarantee that t htr is greater than or equal to zero, so long as the clock rise-time t rc is not more than t rcmax , where t rcmax is not less than 0.15t tr . transmitter delay t dtr ???0.8t???? e e. to allow data to be clocked out on a fa lling edge, the delay is spec ified with respect to the rising edge of the clock signal and t, always giving the receiver sufficient setup time. hold time t htr 0??????? d receiver setup time t sr ?????0.2t r ?? f f. the data setup and hold time must not be less t han the specified receiver setup and hold time. hold time t hr ?????0?? f
document number: 002-15054 rev. *i page 36 of 94 advance cyw43570 note: the time periods specified in figure 17 and figure 18 are defined by the transmitter speed. the receiver specifications must match transmitter performance. figure 17. i 2 s transmitter timing figure 18. i 2 s receiver timing sd ? and ? ws sck v l = ? 0.8v t lc > 0.35t t rc * t hc > 0.35t t v h = ? 2.0v t htr > 0 t otr < 0.8t t ? = ? clock ? period t tr = ? minimum ? allowed ? clock ? period ? for ? transmitter t ? = ? t tr * ? t rc is ? only ? relevant ? for ? transmitters ? in ? slave ? mode. sd ? and ? ws sck v l = ? 0.8v t lc > 0.35t t hc > 0.35 t v h = ? 2.0v t hr > 0 t sr > 0.2t t ? = ? clock ? period t r = ? minimum ? allowed ? clock ? period ? for ? transmitter t ? > ? t r
document number: 002-15054 rev. *i page 37 of 94 advance cyw43570 8. wlan global functions 8.1 wlan cpu and memory subsystem the cyw43570 wlan section includes an integrated arm cortex-r 4 32-bit processor with internal ram and rom. the arm cortex- r4 is a low-power processor that features low gate count, low interrupt latency, and low-cost debug capabilities. it is intende d for deeply embedded applications that require fa st interrupt response features. delivering more than 30% performance gain over arm7tdmi, the arm cortex-r4 implements the arm v7-r architecture with suppo rt for the thumb-2 instruction set. at 0.19 w/mhz, the cortex-r4 is the most powe r efficient general-purpose microprocessor available, outperforming 8- and 16-bit devices on mips/ w. it supports integrated sleep modes. using multiple technologies to reduce cost, the arm cortex-r4 of fers improved memory utilization, reduced pin overhead, and reduced silicon area. it supports independent buses for code and data access (icode/dcode and system buses), and extensive debug features including real time trace of program execution. on-chip memory for the cpu includes 768 kb sram and 640 kb rom. 8.2 one-time programmable memory various hardware configuration parameters may be stored in an inte rnal one-time programmable (otp) memory, which is read by the system software after device reset. in additi on, customer-specific parameters, including the system vendor id and the mac addre ss can be stored, depending on the specific board design. up to 484 bytes of user-accessible otp are available. the initial state of all bits in an unprogra mmed otp device is 0. after any bit is pr ogrammed to a 1, it cannot be reprogrammed to 0. the entire otp array can be programmed in a single write cycle using a utility provided with the cypress wlan manufacturing tes t tools. alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state can be altered during each programming cycle. prior to otp programming, all values should be verified using th e appropriate editable nvram.txt file, which is provided with t he reference board design package.
document number: 002-15054 rev. *i page 38 of 94 advance cyw43570 8.3 gpio interface the wlan section of the cyw43570 supports 16 gpios. upon power up and reset, these pins become tris tated. subsequently, they can be programmed to be either input or output pins vi a the gpio control register. in add ition, the gpio pins can be assigned to various other functions. table 17. strapping options pcie pad names fcbga strapping options default chip internal pulls description gpio_0 y ? ? ? gpio_1 y ? ? ? gpio_2 y ? ? ? gpio_3 y ? ? ? gpio_4 y sprom_present/ 0 1: sprom is present 0: sprom is absent (default is 0) applicable in pcie host mode. gpio_5 y sflash_present 0 1: sflash is present 0: sflash is absent (default is 0) gpio_6 y ? ? ? gpio_7 y ? ? ? gpio_[8:10 ] y strap_host_ifc_ 1 1 together strap_host_ifc [3], [2], and [1] is used to select interfaces: gpio_11 y ? ? ? gpio_12 y default 0 resource mode init in alp clock mode only. gpio_13 y ? ? ? gpio_14 y ? ? ? gpio_15 y ? ? ? gpio10 gpio9 gpio8 wlan host selected bluetooth interprets 0 1 1 pcie (default only for b0, b1, c0 pkg_opt1/fcbga-pc ie) btuart or btusb (11d+11phy) //bt tports stand alone.
document number: 002-15054 rev. *i page 39 of 94 advance cyw43570 9. pci express interface the pci express (pcie) core on the cyw43 570 is a high-performance serial i/o interconn ect that is protocol compliant and electr ically compatible with the pci express base specification v2.0 . this core contains all the necessary blocks, including logi cal and electrical functional subblocks to perform pcie functionality and maintain high-speed links, using existing pci system configuration softw are implementations without modification. organization of the pcie core is in logi cal layers: transaction layer, data link layer, and physical layer, as shown in figure 19 . a configuration or link management block is provided for enumerating the pcie config uration space and supporting generation and reception of system manag ement messages by commun icating with pcie layers. each layer is partitioned into dedicated transmit and receive units that allow point-to-point communication between the host an d cyw43570 device. the transmit side processes outbound packets wh ereas the receive side processes inbound packets. packets are formed and generated in the transaction and data link laye r for transmission onto the high-speed links and onto the receivi ng device. a header is added at the beginning to indicate the packet type and any other optional fields. figure 19. pci express layer model 9.1 transaction layer interface the pcie core employs a packet-based protocol to transfer data between the host and cyw43570 device, delivering new levels of performance and features. the upper layer of the pcie is the tr ansaction layer. the transaction layer is primarily responsible for assembly and disassembly of transaction layer packets (tlps). tlp structure contains header, data payload, and end-to-end crc (ecrc) fields, which are used to communicate transactio ns, such as read and write requests and other events. a pipelined full split-transaction protocol is implemented in this layer to maximize efficient communication between devices wi th credit- based flow control of tlp, which eliminates wasted link bandwidth due to retries. 9.2 data link layer the data link layer serves as an intermediate stage between the transaction layer and the physical layer. its primary responsib ility is to provide reliable, efficient mechanism for the exchange of tlps between two directly connected components on the link. servic es provided by the data link layer include data exchange, initia lization, error detection and correction, and retry services. the data link layer packets (dllps) are generat ed and consumed by the data link layer. dllps are the mechanism used to transfer link management information between data link layers of the two directly connected components on the link, including tlp acknow l- edgement, power management, and flow control. transaction layer data link layer hardware/software interface physical layer logical subblock electrical subblock transaction layer data link layer hardware/software interface physical layer logical subblock electrical subblock tx tx rx rx
document number: 002-15054 rev. *i page 40 of 94 advance cyw43570 9.3 physical layer the physical layer of the pcie provides a handshake mechanism between the data link layer and the high-speed signaling used for link data interchange. th is layer is divided into the logi cal and electrical functional subb locks. both subblocks have dedicate d transmit and receive units that allow for point-to- point communication between the host and cy w43570 device. the transmit section prepar es outgoing information passed from the data link layer for transmi ssion, and the receiver section identifies and prepares receive d information before passing it to the data link layer. this proc ess involves link initialization, configuration, scrambler, and data conversion into a specific format. 9.4 logical subblock the logical sub block primary functions are to prepare outgoing data from the data link layer for transmission and identify rec eived data before passing it to the data link layer. 9.5 scrambler/descrambler this pcie phy component generates pseudo-ra ndom sequence for scrambling of data byte s and the idle sequence. on the transmit side, scrambling is applied to characters prior to the 8b/10b enc oding. on the receive side, descrambling is applied to charact ers after 8b/10b decoding. scrambling may be disabled in polling and recovery for testing and debugging purposes. 9.6 8b/10b encoder/decoder the pcie core on the cyw43570 uses an 8b/10b encoder/decoder scheme to provide dc balancing, synchronizing clock and data recovery, and error detection. the transmission code is specified in the ansi x3.230-1994, clause 11 and in ieee 802.3z, 36.2.4 . using this scheme, 8-bit data characters are treated as 3 bits and 5 bits mapped onto a 4-bit code group and a 6-bit code group , respectively. the control bit in conjunction with the data characte r is used to identify when to encode one of the twelve speci al symbols included in the 8b/10b transmission code. these code groups are co ncatenated to form a 10-bit symbol, which is then transmitted serially. special symbols are used for link management, frame tlps, and dllps, allowing these packets to be quickly identified and easily distinguished. 9.7 elastic fifo an elastic fifo is implemented in the receiver side to compens ate for the differences between the transmit clock domain and the receive clock domain, with worse case clock frequency specified at 600 ppm tolerance. as a result, the transmit and receive clo cks can shift one clock every 1666 clo cks. in addition, the fi fo adaptively ad justs the elastic level bas ed on the rela tive frequen cy difference of the write and read clock. this technique reduces the elastic fifo size and the average receiver latency by half. 9.8 electrical subblock the high-speed signals utilize the common mode logic (cml) signa ling interface with on-chip term ination and de-emphasis for bes t- in-class signal integrity. a de-emphasis technique is employed to reduce the effects of intersymbol interference (isi) due to t he interconnect by optimizing voltage and timing margins for worst case channel loss. this results in a maximally open ?eye? at th e detection point, thereby allowing the receiver to receive data with acceptable bit-error rate (ber). to further minimize isi, multiple bits of the same polarity that are output in succession are de-emphasized. subsequent same bi ts are reduced by a factor of 3.5 db in power. th is amount is specified by pcie to allow for maximum interoperability while minimizing the complexity of controlling the de-emphasis values. the high-speed interface requires ac coupling on the transmit side to elimina te the dc common mode voltage from the receiver. the range of ac capacitance allowed is 75 nf to 200 nf. 9.9 configuration space the pcie function in the cyw43570 implements the configuration s pace as defined in the pci express base specification v2.0 .
document number: 002-15054 rev. *i page 41 of 94 advance cyw43570 10. wlan mac and phy 10.1 ieee 802.11ac draft mac the cyw43570 wlan mac is designed to support high-throughput operation with low-power consum ption. it does so without compromising the bluetooth coexis tence policies, thereby enabling optimal performance over both net works. in addi tion, several power saving modes have been implemented that allow the mac to consume very little power while maintaining network-wide timing synchronization. the architecture diagram of the mac is shown in figure 20 . the following sections provide an overview of the important modules in the mac. figure 20. wlan mac architecture the cyw43570 wlan media access controller (mac) supports feat ures specified in the ieee 802.11 base standard, and amended by ieee 802.11n. the key mac features include: enhanced mac for su pporting ieee 802.11ac draft features transmission and reception of aggregated mpdus (a-mpdu) for high throughput (ht) support for power management schemes, including wmm power-s ave, power-save multi-poll (psmp) and multiphase psmp operation support for immediate ack and block-ack policies interframe space timing support, including rifs support for rts/cts and cts-to-self frame sequences for protecting frame exchanges back-off counters in hardware for supporting multiple priorities as specified in the wmm specification timing synchronization function (tsf), network allocation vector (n av) maintenance, and target b eacon transmission time (tbtt) generation in hardware hardware offload for aes-ccmp, legacy wpa tkip, legacy wep ciphers, wapi, and support for key management support for coexistence with bluetooth and other external radios programmable independent basic service set (ibss) or infrastructure basic service set functionality statistics counters for mib support pmq ifs backoff, btcx tsf nav ext?ihr tx_fifo (32 kb) rx_fifo (10 kb) txe tx a-mpdu rxe rx a-mpdu shared memory (6 kb) psm ucode memory wep tkip,aes, wapi psm embedded cpu interface host registers, dma engines shm bus mac?phy interface ihr bus
document number: 002-15054 rev. *i page 42 of 94 advance cyw43570 10.1.1 psm the programmable state machine (psm) is a mi cro-coded engine, which provides most of the low-level control to the hardware, to implement the ieee 802.11 sp ecification. it is a microcontroll er that is highl y optimized for flow control operations, which ar e predom- inant in implementations of communication protocols. the inst ruction set and fundamental operations are simple and general, whi ch allows algorithms to be optimized until very late in the design process. it also allows for changes to the algorithms to track evolving ieee 802.11 specifications. the psm fetches instructions from the microc ode memory. it uses the shared memory to obtain operands for instructions, as a dat a store, and to exchange data bet ween both the host and the mac data pipeline (via the shm bus). the psm also uses a scratchpad memory (similar to a register bank) to stor e frequently accessed and temporary variables. the psm exercises fine-grained control over the hardware engines, by programming internal hardw are registers (i hr). these ihrs are co-located with the hardw are functions they control, and are a ccessed by the psm via the ihr bus. the psm fetches instructions from the micr ocode memory using an address determined by the program counter, instruction literal, or a program stack. for alu operations t he operands are obtained from shared memory, scratchpad, ihrs, or instruction literals, and the results are written into the s hared memory, scratchpad, or ihrs. there are two basic branch instructions: cond itional branches and alu based branches. to better support the many decision point s in the ieee 802.11 algorithms, branches c an depend on either a readily available signals from the hardware modules (branch cond ition signals are available to the psm without polling the ihrs), or on the results of alu operations. 10.1.2 wep the wired equivalent privacy (wep) engine encapsulates all the ha rdware accelerators to perform the encryption and decryption, and mic computation and verification. the accelerators implement th e following cipher al gorithms: legacy wep, wpa tkip, wpa2 aes- ccmp. the psm determines, based on the frame type and association info rmation, the appropriate cipher algorithm to be used. it suppli es the keys to the hardware engines from an on-chip key table. the wep interfaces with the txe to encrypt and compute the mic on transmit frames, and the rxe to decrypt and verify the mic on receive frames. 10.1.3 txe the transmit engine (txe) constitutes the transmit data path of the mac. it coordinates the dma engines to store the transmit f rames in the txfifo. it interfaces with wep module to encrypt frames , and transfers the frames acro ss the mac-phy interface at the appropriate time determined by the channel access mechanisms. the data received from the dma engines are stored in transmit fi fos. the mac supports multiple logical queues to support traffi c streams that have different qos priority requirements. the psm uses the channel access information from the ifs module to sched ule a queue from which the next frame is transmitted. once the fram e is scheduled, the txe hardware transmits the frame based on a precise timing trigger received from the ifs module. the txe module also contains the hardware t hat allows the rapid assembly of mpdus in to an a-mpdu for tr ansmission. the hardware module aggregates the encrypted mpdus by adding appropriate headers and pad delimiters as needed. 10.1.4 rxe the receive engine (rxe) constitutes the receive data path of t he mac. it interfaces with the dma engine to drain the received frames from the rxfifo. it transfers bytes across the mac-phy interfac e and interfaces with the wep m odule to decrypt frames. the decrypted data is stored in the rxfifo. the rxe module contains programmable filters that are programmed by the psm to accept or filter frames based on several criteri a such as receiver address, b ssid, and certain frame types. the rxe module also contains the hardware required to detect a-mpdus, parse the headers of t he containers, and disaggregate them into component mpdus.
document number: 002-15054 rev. *i page 43 of 94 advance cyw43570 10.1.5 ifs the ifs module contains the timers required to determine interf rame space timing including rifs timing. it also contains multip le backoff engines required to support prioritized access to the medium as specified by wmm. the interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the phy. these timers provide precise timing to the txe to begin frame transmission. th e txe uses this information to send response frames or perform transmit frame-bursting (rifs or sifs separated, as within a txop). the backoff engines (for each access category) monitor channel ac tivity, in each slot duration, to determine whether to continu e or pause the backoff counters. when the backoff counters reach 0, t he txe gets notified, so that it may commence frame transmissio n. in the event of multiple backoff counters decrementing to 0 at the same time, the hardware resolves the conflict based on polic ies provided by the psm. the ifs module also incorporates hardware that allows the mac to enter a low-power state when operating under the ieee power save mode. in this mode, the mac is in a suspended state with its clock turned off. a sleep time r, whose count value is initial ized by the psm, runs on a slow clock and determines the duration over which the mac remains in this suspended state. once the timer expires the mac is restored to its functi onal state. the psm updates the tsf timer based on the sleep duration ensuring that th e tsf is synchronized to the network. the ifs module also contains th e pta hardware that assists the psm in bluetooth coexistence functions. 10.1.6 tsf the timing synchronization function (tsf) module maintains the tsf timer of the mac. it also ma intains the target beacon trans- mission time (tbtt). the tsf timer hardware, under the control of the psm, is capable of adopting timestamps received from beac on and probe response frames in order to ma intain synchronization with the network. the tsf module also generates trigger signals fo r events that are specified as offsets from the tsf timer, such as uplink and d ownlink transmission times used in psmp. 10.1.7 nav the network allocation vector (nav) timer module is responsible for maintaining the nav information conveyed through the durati on field of mac frames. this ensures that the mac complies with the protection me chanisms specified in the standard. the hardware, under the control of the psm, maintains the nav ti mer and updates the timer appropriately based on received frame s. this timing information is provided to the ifs module, which uses it as a virtual carrier-sense indication. 10.1.8 mac-phy interface the mac-phy interface consists of a data path interface to e xchange rx/tx data from/to the phy. in addition, there is an programming interface, which can be controlled either by the host or the psm to configure and control the phy.
document number: 002-15054 rev. *i page 44 of 94 advance cyw43570 10.2 ieee 802.11ac draft phy the cyw43570 wlan digital phy is designed to comply with i eee 802.11ac draft and ieee 802.11 a/b/g/n dual-stream specifica- tions to provide wireless lan connectivity supporting data rates fr om 1 mbps to 866.7 mbps for low-power, high-performance hand held applications. the phy has been designed to work in the presence of interferen ce, radio nonlinearity, and various other impairments. it incorp orates optimized implementations of the filters, fft and viterbi decoder algorithms. efficien t algorithms have been designed to achiev e maximum throughput and reliability, including algorithms for carri er sense/rejection, frequency/phase/timing acquisition and tr acking, channel estimation and tracking. the phy receiver also contains a robust ieee 802.11b demodulator. the phy carrier sense has been tuned to provide high throughput for ieee 802. 11g/11b hybrid networks with bluetooth coexistence. the key phy features include: programmable data rates from mcs0?15 in 20 mhz, 40 mhz, and 80 mhz channels, as specif ied in ieee 802.11ac draft supports optional short gi and green field modes in tx and rx tx and rx ldpc for improved range and power efficiency beamforming support all scrambling, encoding, forward error correction, and modulation in the transmit direction and inverse operations in the rece ive direction. supports ieee 802.11h/k for worldwid e operation advanced algorithms for low power, enhan ced sensitivity, range, and reliability algorithms to improve performance in presence of bluetooth closed loop transmit power control digital rf chip calibration algorithms to handle cmos rf chip non-idealities on-the-fly channel frequency and transmit power selection supports per packet rx antenna diversity available per-packet channel quality and signal strength measurements designed to meet fcc and other wo rldwide regulatory requirements figure 21. wlan phy block diagram filters ? and ? radio ? comp frequency ? and ? timing ? synch carrier ? sense, ? agc, ? and ? rx ? fsm radio ? control ? block common ? logic ? block filters ? and ? radio ? comp afe ? and ? radio mac ? interface buffers ofdm ? demodulate viterbi ? decoder tx ? fsm pa ? comp modulation ? and ? coding modulate/spread frame ? and ? scramble fft/ifft cck/dsss ? demodulate descramble ? and ? deframe coex
document number: 002-15054 rev. *i page 45 of 94 advance cyw43570 11. wlan radio subsystem the cyw43570 includes an integrated dual-band wlan rf transce iver that has been optimized for use in 2.4 ghz and 5 ghz wireless lan systems. it has been designed to provide low-power, low-cost, and robust communications for applications operating in the globally available 2.4 ghz unlicensed ism or 5 ghz u-ni i bands. the transmit and receive sections include all on-chip fi ltering, mixing, and gain control functions. sixteen rf control signals are available (eight per core) to driv e external rf switches and suppo rt optional external power amp lifiers and low-noise amplifiers for each band. see t he reference board schemat ics for further details. 11.1 receiver path the cyw43570 has a wide dynamic range, direct conversion receiver that employs high-order on-chi p channel filtering to ensure reliable operation in the noisy 2.4 ghz ism band or the entire 5 ghz u-nii band. contro l signals are available that can support the use of optional lnas for each band, which can increase the receive sensitivity by several decibels. 11.2 transmitter path baseband data is modulated and upconverted to the 2.4 ghz ism or 5-ghz u-nii bands, respectively. linear on-chip power amplifie rs are included, which are capable of delivering high output powers while meeting ieee 802.11ac and ieee 802.11a/b/g/n specification s without the need for external pas. when using the internal pa s, closed-loop output power control is completely integrated. 11.3 calibration the cyw43570 features dynamic and automatic on-chip calibration to continually compensate for temperature and process variation s across components. these calibration routines are performed period ically in the course of normal radio operation. examples of s ome of the automatic calibration algorithms are baseband filter calibration for optimum tran smit and receive performance, and loft calibration for carrier leakage reduction. in addition, i/q ca libration, r calibration, and vco calibration are performed on-ch ip. no per-board calibration is required in manufacturi ng test, which helps to minimize the test time and cost in large volume product ion.
document number: 002-15054 rev. *i page 46 of 94 advance cyw43570 12. pin diagram an d signal descriptions 12.1 ball maps figure 22 and figure 23 show the fcbga ball map. figure 22. fcbga ball map, 10 mm 10 mm array, 242 balls (top view, 1 of 2) 123456789101112 a vssc gpio_5 pcie_testp pcie_testn pcie_rxtx_ avdd1p2 pcie_rdp0 pcie_rdn0 pcie_tdp0 pcie_tdn0 pcie_refcl kp pcie_refcl kn b bt_usb_dn vssc gpio_6 gpio_2 pcie_avss pcie_avss c bt_usb_dp bt_sf_clk d bt_sf_cs_l e bt_uart_r xd bt_uart_c ts_l bt_i2s_ws otp_vdd33 lpo_in vssc vssc f bt_uart_t xd bt_sf_miso g bt_i2s_clk gpio_4 bt_gpio_4 h bt_sf_mosi bt_i2s_do bt_i2s_di vssc j bt_dev_wa ke bt_host_w ake bt_clk_re q vssc k bt_ifvdd1p 2 bt_vcovdd 1p2 btrgnd btrgnd avdd_bbpl l vddc l bt_lnavdd 1p2 bt_pllvdd1 p2 btrgnd avss_bbpll vddc m btrgnd btrgnd bt_vddo bt_vddc n bt_rf btrgnd btrgnd bt_vddc p bt_pavdd2 p5 btrgnd btrgnd btrgnd vddc vddc r btrgnd btrgnd btrgnd btrgnd btrgnd vssc vssc t wrf_rfin_2 g_core0 rgnd rgnd rgnd rgnd u rgnd rgnd rgnd v wrf_rfout _2g_core0 rgnd rgnd rgnd rgnd rgnd rgnd w rgnd rgnd rgnd wrf_tssi_a _core0 rgnd wrf_gpio_ out_core0 wrf_pfd_g nd1p2 wrf_cp_gn d1p2 wrf_mmd_ gnd1p2 y wrf_pa2g_ vbat_vdd3 p3_core0 rgnd aa wrf_padrv _vbat_vdd 3p3_core0 rgnd ab wrf_pa5g_ vbat_vdd3 p3_core0 rgnd rgnd rgnd rgnd rgnd rgnd rgnd rgnd ac rgnd wrf_rfout _5g_core0 rgnd wrf_rfin_5 g_core0 rgnd wrf_buck_ vdd1p5_co re0 wrf_pfd_v dd1p2 wrf_mmd_ vdd1p2 wrf_synth _vbat_vdd 3p3 rgnd wrf_rfin_2 g_core1 rgnd 123456789101112
document number: 002-15054 rev. *i page 47 of 94 advance cyw43570 figure 23. fcbga ball map, 10 mm 10 mm array, 242 balls (top view, 2 of 2) 12 13 14 15 16 17 18 19 20 21 22 23 pcie_refcl kn pcie_pll_a vdd1p2 pcie_perst _l bt_uart_r ts_l gpio_1 sr_vlx sr_vlx sr_pvss sr_pvss a pcie_avss pcie_clkre q_l pcie_pme_l gpio_0 sr_vddbat a5v b sr_vddbat p5v sr_vddbat p5v c ldo_vdd1p 5 ldo_vdd1p 5 d vssc jtag_sel gpio_3 vssc pmu_avss wl_reg_on vout_ldo3 p3_b vout_ldo3 p3_b e vout_3p3_s ense vout_3p3 vout_3p3 f ldo_vddba t5v ldo_vddba t5v g vssc vssc bt_reg_on vssc gpio_15 gpio_14 vout_cldo h vssc vssc vddio_pmu gpio_12 gpio_13 vout_btld o2p5 j vddc vddc vddio gpio_9 gpio_11 gpio_10 vout_lnld o k vddc vddc vddio_rf rf_sw_ctr l_15 gpio_7 gpio_8 l rf_sw_ctr l_13 rf_sw_ctr l_14 rf_sw_ctr l_12 m vddc rf_sw_ctr l_6 rf_sw_ctr l_11 rf_sw_ctr l_9 n vddc vddc vddc vssc rf_sw_ctr l_7 rf_sw_ctr l_10 p vssc vssc vssc vssc vssc vssc rf_sw_ctr l_5 rf_sw_ctr l_8 rf_sw_ctr l_4 r vssc vssc vssc rf_sw_ctr l_3 t rgnd rgnd rgnd rf_sw_ctr l_0 wrf_xtal_ gnd1p2 wrf_xtal_ out u wrf_loge ng_gnd1p2 rgnd rgnd rgnd rf_sw_ctr l_2 wrf_xtal_ gnd1p2 wrf_xtal_i n v wrf_mmd_ gnd1p2 wrf_vco_ gnd1p2 wrf_gpio_ out_core1 rgnd wrf_tssi_a _core1 rgnd rgnd rf_sw_ctr l_1 wrf_xtal_ gnd1p2 wrf_xtal_ vdd1p2 w wrf_xtal_ gnd1p2 wrf_xtal_ vdd1p5 y rgnd wrf_buck_ vdd1p5_co re1 aa rgnd rgnd rgnd rgnd rgnd rgnd rgnd rgnd rgnd ab rgnd wrf_rfout _2g_core1 rgnd wrf_pa2g_ vbat_vdd3 p3_core1 wrf_padrv _vbat_vdd 3p3_core1 wrf_pa5g_ vbat_vdd3 p3_core1 rgnd rgnd wrf_rfout _5g_core1 rgnd wrf_rfin_5 g_core1 rgnd ac 12 13 14 15 16 17 18 19 20 21 22 23
document number: 002-15054 rev. *i page 48 of 94 advance cyw43570 12.2 pin list table 18. pin list ball pkg net name a1 vssc a2 gpio_5 a4 pcie_testp a5 pcie_testn a6 pcie_rxtx_avdd1p2 a7 pcie_rdp0 a8 pcie_rdn0 a9 pcie_tdp0 a10 pcie_tdn0 a11 pcie_refclkp a12 pcie_refclkn a13 pcie_pll_avdd1p2 a14 pcie_perst_l a15 bt_uart_rts_l a16 gpio_1 a20 sr_vlx a21 sr_vlx a22 sr_pvss a23 sr_pvss b1 bt_usb_dn b2 vssc b3 gpio_6 b4 gpio_2 b9 pcie_avss b12 pcie_avss b14 pcie_clkreq_l b16 pcie_pme_l b17 gpio_0 b23 sr_vddbata5v c1 bt_usb_dp c2 bt_sf_clk c22 sr_vddbatp5v c23 sr_vddbatp5v d2 bt_sf_cs_l d22 ldo_vdd1p5 d23 ldo_vdd1p5 e1 bt_uart_rxd e2 bt_uart_cts_l e5 bt_i2s_ws e6 otp_vdd33 e7 lpo_in e11 vssc e12 vssc e13 jtag_sel e14 gpio_3 e16 vssc e17 pmu_avss e18 wl_reg_on e22 vout_ldo3p3_b e23 vout_ldo3p3_b f2 bt_uart_txd f5 bt_sf_miso f19 vout_3p3_sense f22 vout_3p3 f23 vout_3p3 g1 bt_i2s_clk g2 gpio_4 g5 bt_gpio_4 g22 ldo_vddbat5v g23 ldo_vddbat5v h5 bt_sf_mosi h8 bt_i2s_do h10 bt_i2s_di h12 vssc h13 vssc h15 bt_reg_on h16 vssc h19 gpio_15 h22 gpio_14 h23 vout_cldo j1 bt_dev_wake j2 bt_host_wake j5 bt_clk_req j12 vssc j14 vssc j16 vddio_pmu j19 gpio_12 j22 gpio_13 j23 vout_btldo2p5 k1 bt_ifvdd1p2 k2 bt_vcovdd1p2 k5 btrgnd k8 btrgnd k10 avdd_bbpll table 18. pin list (cont.) ball pkg net name
document number: 002-15054 rev. *i page 49 of 94 advance cyw43570 k12 vddc k14 vddc k16 vddio k19 gpio_9 k20 gpio_11 k22 gpio_10 k23 vout_lnldo l1 bt_lnavdd1p2 l2 bt_pllvdd1p2 l8 btrgnd l9 avss_bbpll l11 vddc l14 vddc l15 vddc l16 vddio_rf l19 rf_sw_ctrl_15 l22 gpio_7 l23 gpio_8 m2 btrgnd m5 btrgnd m8 bt_vddo m10 bt_vddc m19 rf_sw_ctrl_13 m22 rf_sw_ctrl_14 m23 rf_sw_ctrl_12 n1 bt_rf n5 btrgnd n8 btrgnd n10 bt_vddc n15 vddc n19 rf_sw_ctrl_6 n22 rf_sw_ctrl_11 n23 rf_sw_ctrl_9 p1 bt_pavdd2p5 p5 btrgnd p8 btrgnd p10 btrgnd p11 vddc p12 vddc p14 vddc p15 vddc p16 vssc table 18. pin list (cont.) ball pkg net name p19 rf_sw_ctrl_7 p22 rf_sw_ctrl_10 r1 btrgnd r2 btrgnd r5 btrgnd r7 btrgnd r9 btrgnd r11 vssc r12 vssc r13 vssc r14 vssc r15 vssc r16 vssc r17 vssc r19 rf_sw_ctrl_5 r22 rf_sw_ctrl_8 r23 rf_sw_ctrl_4 t1 wrf_rfin_2g_core0 t2 rgnd t5 rgnd t7 rgnd t10 rgnd t13 vssc t15 vssc t16 vssc t19 rf_sw_ctrl_3 u1 rgnd u2 rgnd u5 rgnd u13 rgnd u16 rgnd u17 rgnd u19 rf_sw_ctrl_0 u22 wrf_xtal_gnd1p2 u23 wrf_xtal_out v1 wrf_rfout_2g_core0 v2 rgnd v5 rgnd v6 rgnd v7 rgnd v8 rgnd v9 rgnd table 18. pin list (cont.) ball pkg net name
document number: 002-15054 rev. *i page 50 of 94 advance cyw43570 v13 wrf_logeng_gnd1p2 v16 rgnd v17 rgnd v18 rgnd v19 rf_sw_ctrl_2 v22 wrf_xtal_gnd1p2 v23 wrf_xtal_in w1 rgnd w5 rgnd w6 rgnd w7 wrf_tssi_a_core0 w8 rgnd w9 wrf_gpio_out_core0 w10 wrf_pfd_gnd1p2 w11 wrf_cp_gnd1p2 w12 wrf_mmd_gnd1p2 w13 wrf_vco_gnd1p2 w14 wrf_gpio_out_core1 w15 rgnd w16 wrf_tssi_a_core1 w17 rgnd w18 rgnd w19 rf_sw_ctrl_1 w22 wrf_xtal_gnd1p2 w23 wrf_xtal_vdd1p2 y1 wrf_pa2g_vbat_vdd3p3_core0 y2 rgnd y22 wrf_xtal_gnd1p2 y23 wrf_xtal_vdd1p5 aa1 wrf_padrv_vbat_vdd3p3_core0 aa2 rgnd aa22 rgnd aa23 wrf_buck_vdd1p5_core1 ab1 wrf_pa5g_vbat_vdd3p3_core0 ab2 rgnd ab4 rgnd ab5 rgnd ab7 rgnd ab8 rgnd ab9 rgnd ab10 rgnd ab11 rgnd table 18. pin list (cont.) ball pkg net name ab13 rgnd ab15 rgnd ab16 rgnd ab18 rgnd ab19 rgnd ab20 rgnd ab21 rgnd ab22 rgnd ab23 rgnd ac1 rgnd ac2 wrf_rfout_5g_core0 ac3 rgnd ac4 wrf_rfin_5g_core0 ac5 rgnd ac6 wrf_buck_vdd1p5_core0 ac7 wrf_pfd_vdd1p2 ac8 wrf_mmd_vdd1p2 ac9 wrf_synth_vbat_vdd3p3 ac10 rgnd ac11 wrf_rfin_2g_core1 ac12 rgnd ac13 wrf_rfout_2g_core1 ac14 rgnd ac15 wrf_pa2g_vbat_vdd3p3_core1 ac16 wrf_padrv_vbat_vdd3p3_core1 ac17 wrf_pa5g_vbat_vdd3p3_core1 ac18 rgnd ac19 rgnd ac20 wrf_rfout_5g_core1 ac21 rgnd ac22 wrf_rfin_5g_core1 ac23 rgnd table 18. pin list (cont.) ball pkg net name
document number: 002-15054 rev. *i page 51 of 94 advance cyw43570 12.3 signal descriptions the signal name, type, and description of each pin in the cyw43570 is listed in table 19 . the symbols shown under type indicate pin directions (i/o = bidirectional, i = input, o = output) and th e internal pull-up/pull-down characteristics (pu = weak inter nal pull-up resistor and pd = weak internal pull-down resistor), if any. table 19. signal descriptions ball signal name type description wlan receive rf signal interface t1 wrf_rfin_2g_core0 i 2.4 ghz wlan core0 receiver input. ac11 wrf_rfin_2g_core1 i 2.4 ghz wlan core1 receiver input. ac4 wrf_rfin_5g_core0 i 5 ghz wlan core0 receiver input. ac22 wrf_rfin_5g_core1 i 5 ghz wlan core1 receiver input. v1 wrf_rfout_2g_core0 o 2.4 ghz wlan core0 pa output. ac13 wrf_rfout_2g_core1 o 2.4 ghz wlan core1 pa output. ac2 wrf_rfout_5g_core0 o 5 ghz wlan core0 pa output. ac20 wrf_rfout_5g_core1 o 5 ghz wlan core1 pa output. w7 wrf_tssi_a_core0 i 5 ghz tssi core0 input from an optional external power amplifier/power detector. w16 wrf_tssi_a_core1 i 5 ghz tssi core1 input from an optional external power amplifier/power detector. w9 wrf_gpio_out_core0 i/o gpio or 2.4 ghz tssi core0 input from an optional external power amplifier/power detector. w14 wrf_gpio_out_core1 i/o gpio or 2.4 ghz tssi core1 input from an optional external power amplifier/power detector. rf switch control lines u19 rf_sw_ctrl_0 o programmable rf switch control lines. the control lines are programmable via the driver and nvram file. w19 rf_sw_ctrl_1 o v19 rf_sw_ctrl_2 o t19 rf_sw_ctrl_3 o r23 rf_sw_ctrl_4 o r19 rf_sw_ctrl_5 o n19 rf_sw_ctrl_6 o p19 rf_sw_ctrl_7 o r22 rf_sw_ctrl_8 o n23 rf_sw_ctrl_9 o p22 rf_sw_ctrl_10 o n22 rf_sw_ctrl_11 o m23 rf_sw_ctrl_12 o m19 rf_sw_ctrl_13 o m22 rf_sw_ctrl_14 o l19 rf_sw_ctrl_15 o pcie interface a11 pcie_refclkp i/o 100 ? diff pair clock signal positive. a12 pcie_refclkn i/o 100 ? diff pair clock signal negative. a10 pcie_tdn0 i/o 100 ? diff pair tx data signal negative. a9 pcie_tdp0 i/o 100 ? diff pair tx data signal positive. a7 pcie_rdp0 i/o 100 ? diff pair rx data signal positive.
document number: 002-15054 rev. *i page 52 of 94 advance cyw43570 a8 pcie_rdn0 i/o 100 ? diff pair rx data signal negative. b14 pcie_clkreq_l i/o pcie clock request signal. a14 pcie_perst_l i/o pcie preset signal. a4 pcie_testp i/o 100 ? diff pair. a5 pcie_testn i/o 100 ? diff pair. wlan gpio interface note: the gpio signals can be multiplexed via software and the jtag_sel pin to support other functions. see ta b l e 1 7 for additional details. b17 gpio_0 i/o programmable gpio pins. a16 gpio_1 i/o b4 gpio_2 i/o e14 gpio_3 i/o g2 gpio_4 i/o a2 gpio_5 i/o b3 gpio_6 i/o l22 gpio_7 i/o l23 gpio_8 i/o k19 gpio_9 i/o k22 gpio_10 i/o k20 gpio_11 i/o j19 gpio_12 i/o j22 gpio_13 i/o h22 gpio_14 i/o h19 gpio_15 i/o jtag interface e13 jtag_sel i/o jtag select. this pin must be connected to ground if the jtag interface is not used. clocks e7 lpo_in i external sleep clock input (32.768 khz). j5 bt_clk_req o asserts when wlan wants the host to turn on the reference clock. u23 wrf_xtal_out o xtal oscillator output. v23 wrf_xtal_in i xtal oscillator input. bluetooth transceiver n1 bt_rf o bluetooth rf input/output. c2 bt_sf_clk i sflash_clk. d2 bt_sf_cs_l i/o sflash_csn. f5 bt_sf_miso i/o sflash mast er input, slave output. h5 bt_sf_mosi i/o sflash master output, slave input. bluetooth usb interface b1 bt_usb_dn i/o usb (host) data negative. negative terminal of the usb trans- ceiver. c1 bt_usb_dp i/o usb (host) data positive. positive terminal of the usb trans- ceiver. table 19. signal descriptions (cont.) ball signal name type description
document number: 002-15054 rev. *i page 53 of 94 advance cyw43570 bluetooth uart e2 bt_uart_cts_l i uart clear-t o-send. active-low clear-to- send signal for the hci uart interface. a15 bt_uart_rts_l o uart request-to-send. active-low request-to-send signal for the hci uart interface. bt led control pin. e1 bt_uart_rxd i uart serial input. serial data input for the hci uart interface. f2 bt_uart_txd o uart serial output. se rial data output for the hci uart interface. bluetooth i 2 s g1 bt_i2s_clk i/o i 2 s clock, can be master (output) or slave (input). h8 bt_i2s_do i/o i 2 s data output. h10 bt_i2s_di i/o i 2 s data input. e5 bt_i2s_ws i/o i 2 s ws; can be master (output) or slave (input). bluetooth gpio g5 bt_gpio_4 i/o bluetooth general-purpose i/o. miscellaneous e18 wl_reg_on i used by pmu to power up or power down the internal cyw43570 regulators used by the wlan section. also, when deasserted, this pin holds the wlan section in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. h15 bt_reg_on i used by pmu to power up or power down the internal cyw43570 regulators used by t he bluetooth section. also, when deasserted, this pin holds the bluet ooth section in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. j1 bt_dev_wake i/o bluetooth dev_wake. j2 bt_host_wake i/o bluetooth host_wake. integrated voltage regulators b23 sr_vddbata5v i quiet vbat. c22, c23 sr_vddbatp5v i power vbat. a20, a21 sr_vlx o cbuck switching regulator output. refer to table 33 on page 74 for details of the inductor and capacitor required on this output. d22, d23 ldo_vdd1p5 i lnldo input. g22, g23 ldo_vddbat5v i ldo vbat. y23 wrf_xtal_vdd1p5 i xtal ldo input (1.35v). w23 wrf_xtal_vdd1p2 o xtal ldo output (1.2v). k23 vout_lnldo o output of lnldo. h23 vout_cldo o output of core ldo. j23 vout_ldo2p5 o 2.5v ldo. connects to a 2.2 ? f bypass capacitor to gnd. e22, e23 vout_ldo3p3_b o 3.3v ldo. f22, f23 vout_3p3 o ldo 3.3v output. f19 vout_3p3_sense o voltage sense pin for ldo 3.3v output. bluetooth supplies p1 bt_pavdd2p5 pwr bluetooth pa power supply. l1 bt_lnavdd1p2 pwr bluetooth lna power supply. table 19. signal descriptions (cont.) ball signal name type description
document number: 002-15054 rev. *i page 54 of 94 advance cyw43570 k1 bt_ifvdd1p2 pwr bluetooth if block power supply. l2 bt_pllvdd1p2 pwr bluetooth rf pll power supply. k2 bt_vcovdd1p2 pwr bluetooth rf power supply. m8 bt_vddo pwr core supply. m10, n10 bt_vddc pwr 1.2 v core supply for bt. wlan supplies ac6 wrf_buck_vdd1p5_core0 pwr internal capacitor-less core0 ldo supply. aa23 wrf_buck_vdd1p5_core1 pwr internal capacitor-less core1 ldo supply. ac9 wrf_synth_vbat_vdd3p3 pw r synth vdd 3.3v supply. aa1 wrf_padrv_vbat_vdd3p3_ core0 pwr core0 pa driver vbat supply. ac16 wrf_padrv_vbat_vdd3p3_ core1 pwr core1 pa driver vbat supply. ab1 wrf_pa5g_vbat_vdd3p3_ core0 pwr 5 ghz core0 pa 3.3v vbat supply. ac17 wrf_pa5g_vbat_vdd3p3_ core1 pwr 5 ghz core1 pa 3.3v vbat supply. y1 wrf_pa2g_vbat_vdd3p3_ core0 pwr 2 ghz core0 pa 3.3v vbat supply. ac15 wrf_pa2g_vbat_vdd3p3_ core1 pwr 2 ghz core1 pa 3.3v vbat supply. ac8 wrf_mmd_vdd1p2 pwr 1.2v supply. ac7 wrf_pfd_vdd1p2 pwr 1.2v supply. miscellaneous supplies e6 otp_vdd33 pwr otp 3.3v supply. k12, k14, l11, l14, l15, n15, p11, p12, p14, p15 vddc pwr 1.2v core supply for wlan. k16 vddio pwr 1.8v?3.3v supply for wlan . must be directly connected to pmu_vddio on the pcb. m10, n10 bt_vddc pwr 1.2 v core supply for bt. k10 avdd_bbpll pwr baseband pll supply j16 vddio_pmu pwr 1.8v?3.3v supply for pmu controls. must be directly connected to vddio on the pcb. l16 vddio_rf pwr io supply for rf switch control pads (3.3v). a13 pcie_pll_avdd1p2 pwr 1.2 v supply for pcie pll. a6 pcie_rxtx_avdd1p2 pwr 1.2v supply for pcie tx and rx. b16 pcie_pme_l od pci power management ev ent output. used to request a change in the device or system power state. the assertion and deassertion of this signal is asynchronous to the pcie reference clock. this signal has an open-drain output structure, as per the pci bus local bus specification, revision 2.3 . ground u22, v22, w22, y22 wrf_xtal_gnd1p2 gnd xtal ground. v13 wrf_logeng_gnd1p2 gnd logen ground. table 19. signal descriptions (cont.) ball signal name type description
document number: 002-15054 rev. *i page 55 of 94 advance cyw43570 w13 wrf_vco_gnd1p2 gnd vco ground. w12 wrf_mmd_gnd1p2 gnd ground. w11 wrf_cp_gnd1p2 gnd ground. w10 wrf_pfd_gnd1p2 gnd ground. a1, b2, e11, e12, e16, h12, h13, h16, j12, j14, p16, r11? r17, t13, t15, t16 vssc gnd core ground for wlan. a22, a23 sr_pvss gnd power ground. e17 pmu_avss gnd quiet ground. l9 avss_bbpll gnd baseband pll ground. t2, t5, t7, t10, u1, u2, u5, u13, u16, u17, v2, v5?v9, v16?v18, w1, w5, w6, w8, w15, w17, w18, y2, aa2, aa22, ab2, ab4, ab5, ab7? ab11, ab13, ab15, ab16, ab18? ab23, ac1, ac3, ac5, ac10, ac12, ac14, ac18, ac19, ac21, ac23 rgnd gnd ground. k5, k8, l8, m2, m5, n5, n8, p5, p8, p10, r1, r2, r5, r7, r9 btrgnd gnd ground. b9,b12 pcie_avss gnd pcie ground. table 19. signal descriptions (cont.) ball signal name type description
document number: 002-15054 rev. *i page 56 of 94 advance cyw43570 12.4 wlan/bt gpio signals and strapping options the pins listed in ta b l e 2 0 are sampled at power-on reset (por) to determine the various operating modes. sampling occurs a few milliseconds after an internal por or deassertion of the external por. after the por, each pin assumes the gpio or alternative function specified in the signal descriptions table. each str apping option pin has an internal pull-up (pu) or pull-down (pd) r esistor that determines the default mode. to change the mode, connect an external pu resistor to vddio or a pd resistor to gnd, using a 10 k ? resistor or less. note: refer to the reference board schematics for more information. table 20. bt gpio functions and strapping options a a. currently, bluetooth headless is only supported with bt_sflash onboard. pin name default function description bt_gpio4 0 1: bt serial flash is present. 0: bt serial flash is absent (default).
document number: 002-15054 rev. *i page 57 of 94 advance cyw43570 13. dc characteristics note: values in this data sheet are design goals and are subject to change based on the results of device characterization. 13.1 absolute maximum ratings caution! the absolute maximum ratings in ta b l e 2 1 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. functional operat ion is not guaranteed under thes e conditions. operation at abso lute maximum conditions for extended periods can advers ely affect long-term reliability of the device. 13.2 environmental ratings the environmental ratings are shown in ta b l e 2 2 . table 21. absolute maximum ratings rating symbol value unit dc supply for vbat a and pa driver supply b a. vbat is the main power supply of the chip. b. voltage transients up to 6.0v for up to 10 seconds, cumulative duration over the lifetime of the device, are allowed. voltage transients as high as 5.5v for up to 250 seconds, cumulative durati on over the lifetime of the device, are allowed. vbat ?0.5 to +6.0 v dc supply voltage for digital i/o vddio ?0.5 to 3.9 v dc supply voltage for rf switch i/os vddio_rf ?0.5 to 3.9 v dc input supply voltage for cldo and lnldo ? ?0.5 to 1.575 v dc supply voltage for rf analog vddrf ?0.5 to 1.32 v dc supply voltage for core vddc ?0.5 to 1.32 v wrf_tcxo_vdd ? ?0.5 to 3.63 v maximum undershoot voltage for i/o c c. duration not to exceed 25% of the duty cycle. v undershoot ?0.5 v maximum overshoot voltage for i/o c v overshoot vddio + 0.5 v maximum junction temperature t j 125 c table 22. environmental ratings characteristic value units conditions/comments ambient temperature (t a ) 0 to +60 c functional operation a a. functionality is guaranteed but specifications require derating at extreme temperatur es; see the specification tables for det ails. storage temperature ?40 to +125 c ? relative humidity less than 60 % storage less than 85 % operation
document number: 002-15054 rev. *i page 58 of 94 advance cyw43570 13.3 recommended operating conditions and dc characteristics note: functional operation is not guarante ed outside of the limits shown in table 23 , and operation outside these limits for extended periods can adversely affect long-term reliability of the device. table 23. recommended operating conditions and dc characteristics parameter symbol value unit minimum typical maximum dc supply voltage for vbat vbat a a. vbat is the main power supply of the chip. 3.0 b b. the cyw43570 is functional acro ss this range of voltages. optimal rf performanc e specified in the data sheet, however, is gua ranteed only for 3.13v < vbat < 3.6v. ?3.6v dc supply voltage for core vdd 1.14 1.2 1.26 v dc supply voltage for rf bl ocks in chip vddrf 1.14 1.2 1.26 v dc supply voltage for tcxo input buffer wrf_tcx- o_vdd 1.62 1.8 1.98 v dc supply voltage for digital i/o vddio, vddio_sd 1.71 ? 3.63 v dc supply voltage for rf switch i/os vddio_rf 3.0 3.3 3.6 v external tssi input tssi 0.15 ? 0.95 v internal por threshold vth_por 0.4 ? 0.7 v other digital i/o pins for vddio = 1.8v: input high voltage vih 0.65 vddio ? ?v input low voltage vil ? ? 0.35 vddio v output high voltage @ 2 ma voh vddio ? 0.45 ? ?v output low voltage @ 2 ma vol ? ?0.45v for vddio = 3.3v: input high voltage vih 2.00 ? ?v input low voltage vil ? ?0.80v output high voltage @ 2 ma voh vddio ? 0.4 ? ?v output low voltage @ 2 ma vol ? ?0.40v rf switch control output pins c c. programmable 2 ma to 16 ma drive strength. default is 10 ma. for vddio_rf = 3.3v: output high voltage @ 2 ma voh vddio ? 0.4 ? ?v output low voltage @ 2 ma vol ? ?0.40v input capacitance c in ? ? 5 pf
document number: 002-15054 rev. *i page 59 of 94 advance cyw43570 14. bluetooth rf specifications note: values in this data sheet are design goals and are subject to change based on the results of device characterization. unless otherwise stated, limit values apply for the conditions specified in ta b l e 2 2 and table 23 . typical values apply for an ambient temperature of +25c. figure 24. rf port location for bluetooth testing note: all bluetooth specifications are measured at the chip port unless otherwise specified. table 24. bluetooth receiver rf specifications parameter conditions minimum typical maximum unit note: the specifications in this table are measured at the chip port output unle ss otherwise specified. general frequency range ? 2402 ? 2480 mhz rx sensitivity gfsk, 0.1% ber, 1 mbps ? ?92 ? dbm ? /4?dqpsk, 0.01% ber, 2 mbps ? ?94 ? dbm 8?dpsk, 0.01% ber, 3 mbps ? ?88 ? dbm input ip3 ? ? ?16 ? dbm maximum input at antenna ? ? ?20 ? dbm rx lo leakage 2.4 ghz band ? ? ?93 ?80.0 dbm interference performance a c/i co-channel gfsk, 0.1% ber ? 8 11 db c/i 1 mhz adjacent channel gfsk, 0.1% ber ? ?7 0 db c/i 2 mhz adjacent channel gfsk, 0.1% ber ? ?38 ?30 db c/i ? 3 mhz adjacent channel gfsk, 0.1% ber ? ?56 ?40 db c/i image channel gfsk, 0.1% ber ? ?31 ?9 db c/i 1 mhz adjacent to image channel gfsk, 0.1% ber ? ?46 ?20 db c/i co-channel ? /4?dqpsk, 0.1% ber ? 9 13 db c/i 1 mhz adjacent channel ? /4?dqpsk, 0.1% ber ? ?11 0 db c/i 2 mhz adjacent channel ? /4?dqpsk, 0.1% ber ? ?39 ?30 db c/i ? 3 mhz adjacent channel ? /4?dqpsk, 0.1% ber ? ?55 ?40 db c/i image channel ? /4?dqpsk, 0.1% ber ? ?23 ?7 db filter bcm43570 antenna ? port rf ? port bt ? rx/tx
document number: 002-15054 rev. *i page 60 of 94 advance cyw43570 c/i 1 mhz adjacent to image channel ? /4?dqpsk, 0.1% ber ? ?43 ?20 db c/i co-channel 8?dpsk, 0.1% ber ? 17 21 db c/i 1 mhz adjacent channel 8?dpsk, 0.1% ber ? ?4 5 db c/i 2 mhz adjacent channel 8?dpsk, 0.1% ber ? ?37 ?25 db c/i ? 3 mhz adjacent channel 8?dpsk, 0.1% ber ? ?53 ?33 db c/i image channel 8?d psk, 0.1% ber ? ?16 0 db c/i 1 mhz adjacent to image channel 8?dpsk, 0.1% ber ? ?37 ?13 db a. the maximum value represents the actual bluetooth specificat ion required for bluetooth qualifica tion as defined in the versio n 4.1 specification. table 25. bluetooth transmitter rf specifications parameter conditions minimum typical maximum unit note: the specifications in this table are measured at the chip port output unless otherwise specified. general frequency range 2402 ? 2480 mhz basic rate (gfsk) tx power at bluetooth ? 12.0 ? dbm qpsk tx power at bluetooth ? 9.0 ? dbm 8psk tx power at bluetooth ? 9.0 ? dbm power control step ? ? 4 8 db note: output power is with tca and tssi enabled. gfsk in-band spurious emissions ?20 dbc bw ? ? 0.93 1 mhz edr in-band spurious emissions 1.0 mhz < |m ? n| < 1.5 mhz m ? n = the frequency range for which the spurious emission is measured relative to the transmit center frequency. ? ?38 ?26.0 dbc 1.5 mhz < |m ? n| < 2.5 mhz ? ?31 ?20.0 dbm |m ? n| ? 2.5 mhz a a. the typical number is measured at 3 mhz offset. ? ?43 ?40.0 dbm out-of-band spur ious emissions 30 mhz to 1 ghz ? ? ? ?36.0 b, c b. the maximum value represents the value required for bluet ooth qualification as defined in the v4.1 specification. c. the spurious emissions during idle mode are the same as specified in table 25 . dbm 1 ghz to 12.75 ghz ? ? ? ?30.0 b, d, e d. specified at the bluetooth antenna port. e. meets this specification us ing a front-end band-pass filter. dbm 1.8 ghz to 1.9 ghz ? ? ? ?47.0 dbm 5.15 ghz to 5.3 ghz ? ? ? ?47.0 dbm gps band spurio us emissions spurious emissions ? ? ?103 ? dbm table 24. bluetooth receiver rf specifications (cont.) parameter conditions minimum typical maximum unit
document number: 002-15054 rev. *i page 61 of 94 advance cyw43570 table 26. local oscillator performance parameter minimum typical maximum unit lo performance lock time ? 72 ? ? s initial carrier frequency tolerance ? 25 75 khz frequency drift dh1 packet ? 8 25 khz dh3 packet ? 8 40 khz dh5 packet ? 8 40 khz drift rate ? 5 20 khz/50 ? s frequency deviation 00001111 sequence in payload a a. this pattern represents an average deviation in payload. 140 155 175 khz 10101010 sequence in payload b b. pattern represents the maximum deviation in payload for 99.9% of all frequency deviations. 115 140 ? khz channel spacing ?1?mhz table 27. ble rf specifications parameter conditions minimum typical maximum unit frequency range ? 2402 ? 2480 mhz rx sense a a. dirty tx is on. gfsk, 0.1% ber, 1 mbps ? ?94 ? dbm tx power b b. ble tx power can be increased to compensate for front-end losses such as bpf, diplexer, switch, etc.). the output is capped a t 12 dbm out. the ble tx power at the antenna port cannot exceed the 10 dbm specification limit. ? ? 8.5 ? dbm mod char: delta f1 average ? 225 255 275 khz mod char: delta f2 max c c. at least 99.9% of all delta f2 max frequency values recorded over 10 packets must be greater than 185 khz. ? ? 99.9 ? % mod char: ratio ? 0.8 0.95 ? %
document number: 002-15054 rev. *i page 62 of 94 advance cyw43570 15. wlan rf specifications 15.1 introduction the cyw43570 includes an integrated dual-band direct conversion radio that supports the 2.4 ghz and the 5 ghz bands. this sectio n describes the rf characteristics of the 2.4 ghz and 5 ghz radios. note: values in this section of the data sheet are design goals and are subject to change based on the results of device characterization. unless otherwise stated, limit values apply for the conditions specified in ta b l e 2 2 and table 23 . typical values apply for an ambient temperature +25c. figure 25. port locations (applies to 2.4 ghz and 5 ghz) 15.2 2.4 ghz band general rf specifications table 28. 2.4 ghz band general rf specifications item condition min. typ. max. unit tx/rx switch time including tx ramp down ? ? 5 ? s rx/tx switch time including tx ramp up ? ? 2 ? s power-up and power-down ramp ti me dsss/cck modulations ? ? < 2 ? s filter cyw43570 rf ? switch (0.5 ? db ? insertion ? loss) antenna ? port rf ? port wlan ? tx wlan ? rx chip port
document number: 002-15054 rev. *i page 63 of 94 advance cyw43570 15.3 wlan 2.4 ghz receiver performance specifications note: the specifications in ta b l e 2 9 are specified at the rf port unl ess otherwise specified. results with fems that are not on the cypress avl are not guaranteed. table 29. wlan 2.4 ghz receiver performance specifications parameter condition/notes min. typ. max. unit frequency range ? 2400 ? 2500 mhz rx sensitivity ieee 802.11b a 1 mbps dsss ? ?98.5 ? dbm 2 mbps dsss ? ?95.4 ? dbm 5.5 mbps dsss ? ?93.4 ? dbm 11 mbps dsss ? ?90.4 ? dbm siso rx sensitivity ieee 802.11g (10% per for 1024 octet psdu) a 6 mbps ofdm ? ?94.4 ? dbm 9 mbps ofdm ? ?93.4 ? dbm 12 mbps ofdm ? ?91.5 ? dbm 18 mbps ofdm ? ?89.3 ? dbm 24 mbps ofdm ? ?86.0 ? dbm 36 mbps ofdm ? ?82.8 ? dbm 48 mbps ofdm ? ?78.4 ? dbm 54 mbps ofdm ? ?77.0 ? dbm mimo rx sensitivity ieee 802.11g (10% per for 1024 octet psdu) a 6 mbps ofdm ? ?95.6 ? dbm/core 9 mbps ofdm ? ?95.4 ? dbm/core 12 mbps ofdm ? ?94.3 ? dbm/core 18 mbps ofdm ? ?92.4 ? dbm/core 24 mbps ofdm ? ?88.9 ? dbm/core 36 mbps ofdm ? ?85.8 ? dbm/core 48 mbps ofdm ? ?81.4 ? dbm/core 54 mbps ofdm ? ?80.0 ? dbm/core siso rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a, b defined for default parameters: gt, 800 ns gi, ldpc coding, and non-stbc. 20 mhz channel spacing for all mcs rates mcs0 ? ?93.6 ? dbm mcs1 ? ?91.0 ? dbm mcs2 ? ?88.7 ? dbm mcs3 ? ?86.2 ? dbm mcs4 ? ?82.7 ? dbm mcs5 ? ?78.6 ? dbm mcs6 ? ?77.2 ? dbm mcs7 ? ?75.4 ? dbm
document number: 002-15054 rev. *i page 64 of 94 advance cyw43570 mimo rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a, b defined for default parameters: gt, 800 ns gi, ldpc coding, and non-stbc. 20 mhz channel spacing for all mcs rates mcs0 ? ?94.8 ? dbm/core mcs1 ? ?93.7 ? dbm/core mcs2 ? ?91.6 ? dbm/core mcs3 ? ?88.9 ? dbm/core mcs4 ? ?85.6 ? dbm/core mcs5 ? ?81.5 ? dbm/core mcs6 ? ?80.3 ? dbm/core mcs7 ? ?78.4 ? dbm/core mcs8 ? ?94.5 ? dbm/core mcs15 ? ?76.2 ? dbm/core siso rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a, b defined for default parameters: gt, 800 ns gi, ldpc coding, and non-stbc. 40 mhz channel spacing for all mcs rates mcs0 ? ?91.1 ? dbm mcs1 ? ?88.5 ? dbm mcs2 ? ?86.0 ? dbm mcs3 ? ?83.5 ? dbm mcs4 ? ?80.1 ? dbm mcs5 ? ?76.3 ? dbm mcs6 ? ?74.4 ? dbm mcs7 ? ?73.1 ? dbm mimo rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a, b defined for default parameters: gt, 800 ns gi, ldpc coding, and non-stbc. 40 mhz channel spacing for all mcs rates mcs0 ? ?93.3 ? dbm/core mcs1 ? ?91.3 ? dbm/core mcs2 ? ?88.9 ? dbm/core mcs3 ? ?86.2 ? dbm/core mcs4 ? ?83.2 ? dbm/core mcs5 ? ?79.2 ? dbm/core mcs6 ? ?77.4 ? dbm/core mcs7 ? ?76.5 ? dbm/core mcs8 ? ?91.7 ? dbm/core mcs15 ? ?73.4 ? dbm/core siso rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a, b defined for default parameters: 800 ns gi and non-stbc 20 mhz channel spacing for all mcs rates mcs0, nss 1 ? ?93.8 ? dbm mcs1, nss 1 ? ?91.1 ? dbm mcs2, nss 1 ? ?89.9 ? dbm mcs3, nss 1 ? ?87.4 ? dbm mcs4, nss 1 ? ?83.6 ? dbm mcs5, nss 1 ? ?79.8 ? dbm mcs6, nss 1 ? ?78.4 ? dbm mcs7, nss 1 ? ?77.1 ? dbm mcs8, nss 1 ? ?72.9 ? dbm mcs9, nss 1 ? ?71.4 ? dbm table 29. wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes min. typ. max. unit
document number: 002-15054 rev. *i page 65 of 94 advance cyw43570 mimo rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a, b defined for default parameters: 800 ns gi and non-stbc 20 mhz channel spacing for all mcs rates mcs0, nss 1 ? ?95.6 ? dbm/core mcs1, nss 1 ? ?93.9 ? dbm/core mcs2, nss 1 ? ?92.6 ? dbm/core mcs3, nss 1 ? ?90.3 ? dbm/core mcs4, nss 1 ? ?87.0 ? dbm/core mcs5, nss 1 ? ?82.7 ? dbm/core mcs6, nss 1 ? ?81.3 ? dbm/core mcs7, nss 1 ? ?80.2 ? dbm/core mcs8, nss 1 ? ?76.3 ? dbm/core mcs9, nss 1 ? ?74.5 ? dbm/core mcs9, nss 2 ? ?71.1 ? dbm/core siso rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a, b defined for default parameters: 800 ns gi and non-stbc. 40 mhz channel spacing for all mcs rates mcs0, nss 1 ? ?91.5 ? dbm mcs1, nss 1 ? ?88.5 ? dbm mcs2, nss 1 ? ?87.1 ? dbm mcs3, nss 1 ? ?84.7 ? dbm mcs4, nss 1 ? ?81.4 ? dbm mcs5, nss 1 ? ?77.2 ? dbm mcs6, nss 1 ? ?75.8 ? dbm mcs7, nss 1 ? ?74.4 ? dbm mcs8, nss 1 ? ?70.4 ? dbm mcs9, nss 1 ? ?68.7 ? dbm mimo rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a, b defined for default parameters: 800 ns gi and non-stbc. 40 mhz channel spacing for all mcs rates mcs0, nss 1 ? ?93.1 ? dbm/core mcs1, nss 1 ? ?91.3 ? dbm/core mcs2, nss 1 ? ?89.7 ? dbm/core mcs3, nss 1 ? ?87.8 ? dbm/core mcs4, nss 1 ? ?84.3 ? dbm/core mcs5, nss 1 ? ?80.2 ? dbm/core mcs6, nss 1 ? ?78.6 ? dbm/core mcs7, nss 1 ? ?77.3 ? dbm/core mcs8, nss 1 ? ?73.6 ? dbm/core mcs9, nss 1 ? ?71.6 ? dbm/core mcs0, nss 2 ? ?91.7 ? dbm/core mcs9, nss 2 ? ?67.7 ? dbm/core in-band static cw jammer immunity (fc ? 8 mhz < fcw < + 8 mhz) rx per < 1%, 54 mbps ofdm, 1000 octet psdu for: (rxsens + 23 db < rxlevel < max input level) ?80 ? ? dbm input in?band ip3 maximum lna gain ? ?15.5 ? dbm minimum lna gain ? ?1.5 ? dbm table 29. wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes min. typ. max. unit
document number: 002-15054 rev. *i page 66 of 94 advance cyw43570 maximum receive level @ 2.4 ghz @ 1, 2 mbps (8% per, 1024 octets) ? ?3.5 ? dbm @ 5.5, 11 mbps (8% per, 1024 octets) ? ?9.5 ? dbm @ 6?54 mbps (10% per, 1024 octets) ? ?9.5 ? dbm @ mcs0?mcs7 rates (10% per, 4095 octets) ? ?9.5 ? dbm @ mcs8?mcs9 rates (10% per, 4095 octets) ??11.5?dbm lpf 3 db bandwidth ? 9 ? 36 mhz adjacent channel rejection-dsss (difference between interfering and desired signal at 8% per for 1024 octet psdu with desired signal level as specified in condition/notes) desired and interfering signal 30 mhz apart 1 mbps dsss ?74 dbm 35 ? ? db 2 mbps dsss ?74 dbm 35 ? ? db desired and interfering signal 25 mhz apart 5.5 mbps dsss ?70 dbm 35 ? ? db 11 mbps dsss ?70 dbm 35 ? ? db adjacent channel rejection-ofdm (difference between interfering and desired signal (25 mhz apart) at 10% per for 1024 octet psdu with desired signal level as specified in condition/notes) 6 mbps ofdm ?79 dbm 16 ? ? db 9 mbps ofdm ?78 dbm 15 ? ? db 12 mbps ofdm ?76 dbm 13 ? ? db 18 mbps ofdm ?74 dbm 11 ? ? db 24 mbps ofdm ?71 dbm 8 ? ? db 36 mbps ofdm ?67 dbm 4 ? ? db 48 mbps ofdm ?63 dbm 0 ? ? db 54 mbps ofdm ?62 dbm ?1 ? ? db adjacent channel rejection mcs0?9 (difference between interfering and desired signal (25 mhz apart) at 10% per for 4096 octet psdu with desired signal level as specified in condition/notes) mcs0 ?79 dbm 16 ? ? db mcs1 ?76 dbm 13 ? ? db mcs2 ?74 dbm 11 ? ? db mcs3 ?71 dbm 8 ? ? db mcs4 ?67 dbm 4 ? ? db mcs5 ?63 dbm 0 ? ? db mcs6 ?62 dbm ?1 ? ? db mcs7 ?61 dbm ?2 ? ? db mcs8 ?59 dbm ?4 ? ? db mcs9 ?57 dbm ?6 ? ? db maximum receiver gain ? ? ? 95 ? db gain control step ? ? ? 3 ? db rssi accuracy c range ?90 dbm to ?30 dbm ?5 ? 5 db range above ?30 dbm ?8 ? 8 db return loss zo = 50 ? , across the dynamic range 10 11.5 13 db receiver cascaded noise figure at maximum gain ? 4.5 ? db a. derate by 1.5 db over the operating temperature range and for voltages from 3.0v to 3.13v. b. sensitivity degradations for alternate settings in mcs modes. mm: 0.5 db drop, and sgi: 2 db drop. c. the minimum and maximum values shown have a 95% confidence level. table 29. wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes min. typ. max. unit
document number: 002-15054 rev. *i page 67 of 94 advance cyw43570 15.4 wlan 2.4 ghz transmitter performance specifications note: the specifications in ta b l e 3 0 are specified at the rf port unl ess otherwise specified. results with fems that are not on the cypress avl are not guaranteed. table 30. wlan 2.4 ghz transmitter performance specifications parameter condition/notes min. typ. max. unit frequency range ? 2400 ? 2500 mhz evm does not exceed tx power at rf port for highest power level setting at 25c with spectral mask and evm compliance a a. derate by 1.5 db over the operating temperature range and for voltages from 3.0v to 3.13v. 802.11b (dsss/cck) ?9 db 18.5 20 ? dbm ofdm, bpsk ?8 db 18 19 ? dbm ofdm, qpsk ?13 db 18 19 ? dbm ofdm, 16-qam ?19 db 16.5 18 ? dbm ofdm, 64-qam (r = 3/4) ?25 db 16.5 18 ? dbm ofdm, 64-qam (r = 5/6) ?28 db 16.5 18 ? dbm ofdm, 256-qam (r = 3/4) ?30 db 15.5 17 ? dbm ofdm, 256-qam (r = 5/6) ?32 db 14.5 16 ? dbm phase noise 40 mhz crystal, integrated from 10 khz to 10 mhz ? 0.45 ? degrees tx power control dynamic range ?10??db closed-loop tx power variation at highest power level setting across full temperature and voltage range. applies across 10 dbm to 20 dbm output power range. ??1.5db carrier suppression ? 15 ? ? dbc gain control step ? ? 0.25 ? db return loss at chip port tx zo = 50 ? ?6?db
document number: 002-15054 rev. *i page 68 of 94 advance cyw43570 15.5 wlan 5 ghz receiver performance specifications note: the specifications in ta b l e 3 1 are specified at the rf port unl ess otherwise specified. results with fems that are not on the cypress avl are not guaranteed. table 31. wlan 5 ghz receiver performance specifications parameter condition/notes min. typ. max. unit frequency range ? 4900 ? 5845 mhz siso rx sensitivity ieee 802.11a (10% per for 1000 octet psdu) a 6 mbps ofdm ? ?94.5 ? dbm 9 mbps ofdm ? ?93.2 ? dbm 12 mbps ofdm ? ?91.3 ? dbm 18 mbps ofdm ? ?89.1 ? dbm 24 mbps ofdm ? ?85.7 ? dbm 36 mbps ofdm ? ?82.4 ? dbm 48 mbps ofdm ? ?78.0 ? dbm 54 mbps ofdm ? ?76.6 ? dbm mimo rx sensitivity ieee 802.11a (10% per for 1024 octet psdu) a 6 mbps ofdm ? ?95.7 ? dbm/core 9 mbps ofdm ? ?95.6 ? dbm/core 12 mbps ofdm ? ?94.1 ? dbm/core 18 mbps ofdm ? ?92.1 ? dbm/core 24 mbps ofdm ? ?89.0 ? dbm/core 36 mbps ofdm ? ?85.7 ? dbm/core 48 mbps ofdm ? ?81.2 ? dbm/core 54 mbps ofdm ? ?79.9 ? dbm/core siso rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a defined for default parameters: gf, 800 ns gi, ldpc coding, and non-stbc. 20 mhz channel spacing for all mcs rates mcs0 ? ?93.3 ? dbm mcs1 ? ?90.9 ? dbm mcs2 ? ?88.7 ? dbm mcs3 ? ?86.1 ? dbm mcs4 ? ?82.5 ? dbm mcs5 ? ?78.4 ? dbm mcs6 ? ?76.9 ? dbm mcs7 ? ?75.1 ? dbm mimo rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a defined for default parameters: gf, 800 ns gi, ldpc coding, and non-stbc. 20 mhz channel spacing for all mcs rates mcs0 ? ?95.8 ? dbm/core mcs1 ? ?93.8 ? dbm/core mcs2 ? ?91.4 ? dbm/core mcs3 ? ?88.7 ? dbm/core mcs4 ? ?85.6 ? dbm/core mcs5 ? ?81.4 ? dbm/core mcs6 ? ?79.8 ? dbm/core mcs7 ? ?78.3 ? dbm/core mcs8 ? ?75.6 ? dbm/core mcs15 ? ?72.7 ? dbm/core
document number: 002-15054 rev. *i page 69 of 94 advance cyw43570 siso rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a defined for default parameters: gf, 800 ns gi, ldpc coding, and non-stbc. 40 mhz channel spacing for all mcs rates mcs0 ? ?91.1 ? dbm mcs1 ? ?88.5 ? dbm mcs2 ? ?86.0 ? dbm mcs3 ? ?83.5 ? dbm mcs4 ? ?80.1 ? dbm mcs5 ? ?76.3 ? dbm mcs6 ? ?74.3 ? dbm mcs7 ? ?72.9 ? dbm mimo rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a defined for default parameters: gf, 800 ns gi, ldpc coding, and non-stbc. 40 mhz channel spacing for all mcs rates mcs0 ? ?92.9 ? dbm/core mcs1 ? ?91.1 ? dbm/core mcs2 ? ?88.7 ? dbm/core mcs3 ? ?86.2 ? dbm/core mcs4 ? ?83.0 ? dbm/core mcs5 ? ?79.2 ? dbm/core mcs6 ? ?77.4 ? dbm/core mcs7 ? ?76.4 ? dbm/core mcs8 ? ?91.9 ? dbm/core mcs15 ? ?73.3 ? dbm/core siso rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a defined for default parameters: 800 ns gi, ldpc coding, and non-stbc. 20 mhz channel spacing for all mcs rates mcs0, nss 1 ? ?93.4 ? dbm mcs1, nss 1 ? ?91.0 ? dbm mcs2, nss 1 ? ?89.7 ? dbm mcs3, nss 1 ? ?87.2 ? dbm mcs4, nss 1 ? ?83.1 ? dbm mcs5, nss 1 ? ?79.5 ? dbm mcs6, nss 1 ? ?78.0 ? dbm mcs7, nss 1 ? ?76.8 ? dbm mcs8, nss 1 ? ?72.3 ? dbm mcs9, nss 1 ? ?70.7 ? dbm table 31. wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes min. typ. max. unit
document number: 002-15054 rev. *i page 70 of 94 advance cyw43570 mimo rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a defined for default parameters: 800 ns gi, ldpc coding, and non-stbc. 20 mhz channel spacing for all mcs rates mcs0, nss 1 ? ?95.7 ? dbm/core mcs1, nss 1 ? ?93.9 ? dbm/core mcs2, nss 1 ? ?92.7 ? dbm/core mcs3, nss 1 ? ?90.3 ? dbm/core mcs4, nss 1 ? ?86.8 ? dbm/core mcs5, nss 1 ? ?82.7 ? dbm/core mcs6, nss 1 ? ?81.4 ? dbm/core mcs7, nss 1 ? ?79.9 ? dbm/core mcs8, nss 1 ? ?75.6 ? dbm/core mcs0, nss 2 ? ?91 ? dbm/core mcs8, nss 2 ? ?67.1 ? dbm/core mcs9, nss 2 ? ?74.1 ? dbm/core siso rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a defined for default parameters: 800 ns gi, ldpc coding, and non-stbc. 40 mhz channel spacing for all mcs rates mcs0, nss 1 ? ?91.5 ? dbm mcs1, nss 1 ? ?88.5 ? dbm mcs2, nss 1 ? ?87.2 ? dbm mcs3, nss 1 ? ?84.6 ? dbm mcs4, nss 1 ? ?81.2 ? dbm mcs5, nss 1 ? ?77.1 ? dbm mcs6, nss 1 ? ?75.6 ? dbm mcs7, nss 1 ? ?74.2 ? dbm mcs8, nss 1 ? ?70.0 ? dbm mcs9, nss 1 ? ?68.2 ? dbm mimo rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a defined for default parameters: 800 ns gi, ldpc coding, and non-stbc. 40 mhz channel spacing for all mcs rates mcs0, nss 1 ? ?93.0 ? dbm/core mcs1, nss 1 ? ?91.2 ? dbm/core mcs2, nss 1 ? ?89.8 ? dbm/core mcs3, nss 1 ? ?87.6 ? dbm/core mcs4, nss 1 ? ?84.1 ? dbm/core mcs5, nss 1 ? ?80.1 ? dbm/core mcs6, nss 1 ? ?78.6 ? dbm/core mcs7, nss 1 ? ?77.3 ? dbm/core mcs8, nss 1 ? ?73.1 ? dbm/core mcs9, nss 1 ? ?71.4 ? dbm/core mcs0, nss 2 ? ?91.8 ? dbm/core mcs9, nss 2 ? ?67.1 ? dbm/core table 31. wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes min. typ. max. unit
document number: 002-15054 rev. *i page 71 of 94 advance cyw43570 siso rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a defined for default parameters: 800 ns gi, ldpc coding, and non-stbc. 80 mhz channel spacing for all mcs rates mcs0, nss 1 ? ?88.7 ? dbm mcs1, nss 1 ? ?85.2 ? dbm mcs2, nss 1 ? ?83.8 ? dbm mcs3, nss 1 ? ?81.2 ? dbm mcs4, nss 1 ? ?77.8 ? dbm mcs5, nss 1 ? ?73.5 ? dbm mcs6, nss 1 ? ?72.2 ? dbm mcs7, nss 1 ? ?70.5 ? dbm mcs8, nss 1 ? ?66.4 ? dbm mcs9, nss 1 ? ?64.1 ? dbm mimo rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a defined for default parameters: 800 ns gi, ldpc coding, and non-stbc. 80 mhz channel spacing for all mcs rates mcs0, nss 1 ? ?90.2 ? dbm/core mcs1, nss 1 ? ?88.0 ? dbm/core mcs2, nss 1 ? ?86.5 ? dbm/core mcs3, nss 1 ? ?84.2 ? dbm/core mcs4, nss 1 ? ?80.7 ? dbm/core mcs5, nss 1 ? ?76.6 ? dbm/core mcs6, nss 1 ? ?75.0 ? dbm/core mcs7, nss 1 ? ?73.4 ? dbm/core mcs8, nss 1 ? ?69.4 ? dbm/core mcs9, nss 1 ? ?67.2 ? dbm/core mcs0, nss 2 ? ?88.2 ? dbm/core mcs9, nss 2 ? ?62.2 ? dbm/core input in-band ip3 maximum lna gain ? ?15.5 ? dbm minimum lna gain ? ?1.5 ? dbm maximum receive level @ 5.24 ghz @ 6, 9, 12 mbps ? ?9.5 ? dbm @ 18, 24, 36, 48, 54 mbps ? ?14.5 ? dbm lpf 3 db bandwidth ? 9 ? 36 mhz adjacent channel rejection (difference between interfering and desired signal (20 mhz apart) at 10% per for 1000 octet psdu with desired signal level as specified in condition/ notes) 6 mbps ofdm ?79 dbm 16 ? ? db 9 mbps ofdm ?78 dbm 15 ? ? db 12 mbps ofdm ?76 dbm 13 ? ? db 18 mbps ofdm ?74 dbm 11 ? ? db 24 mbps ofdm ?71 dbm 8 ? ? db 36 mbps ofdm ?67 dbm 4 ? ? db 48 mbps ofdm ?63 dbm 0 ? ? db 54 mbps ofdm ?62 dbm ?1 ? ? db 65 mbps ofdm ?61 dbm ?2 ? ? db table 31. wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes min. typ. max. unit
document number: 002-15054 rev. *i page 72 of 94 advance cyw43570 (difference between interfering and desired signal (40 mhz apart) at 10% per for 1000 b octet psdu with desired signal level as specified in condition/ notes) 6 mbps ofdm ?78.5 dbm 32 ? ? db 9 mbps ofdm ?77.5 dbm 31 ? ? db 12 mbps ofdm ?75.5 dbm 29 ? ? db 18 mbps ofdm ?73.5 dbm 27 ? ? db 24 mbps ofdm ?70.5 dbm 24 ? ? db 36 mbps ofdm ?66.5 dbm 20 ? ? db 48 mbps ofdm ?62.5 dbm 16 ? ? db 54 mbps ofdm ?61.5 dbm 15 ? ? db 65 mbps ofdm ?60.5 dbm 14 ? ? db maximum receiver gain ? ? 95 ? db gain control step ? ? 3 ? db rssi accuracy c range ?90 dbm to ?30 dbm ?5 ? 5 db range above ?30 dbm ?8 ? 8 db return loss zo = 50 ? , across the dynamic range 10 ? 13 db receiver cascaded noise figure at maximum gain ? 5 ? db a. derate by 1.5 db over the operating temperature range and for voltages from 3.0v to 3.13v. b. for 65 mbps, the size is 4096. c. the minimum and maximum values shown have a 95% confidence level. table 31. wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes min. typ. max. unit
document number: 002-15054 rev. *i page 73 of 94 advance cyw43570 15.6 wlan 5 ghz transmitter performance specifications note: the specifications in ta b l e 3 2 are specified at the rf port unl ess otherwise specified. results with fems that are not on the cypress avl are not guaranteed. table 32. wlan 5 ghz transmitter performance specifications parameter condition/notes min. typ. max. unit frequency range ? 4900 ? 5845 mhz tx power at rf port for highest power level setting at 25c with spectral mask and evm compliance a a. derate by 1.5 db over the operating temperature range and for voltages from 3.0v to 3.13v. ofdm, qpsk ?13 db 17.5 18.5 ? dbm ofdm, 16-qam ?19 db 16 17.5 ? dbm ofdm, 64-qam (r = 3/4) ?25 db 16 17.5 ? dbm ofdm, 64-qam (r = 5/6) ?28 db 16 17.5 ? dbm ofdm, 256-qam (r = 3/4, vht) ?30 db 14 15.5 ? dbm ofdm, 256-qam (r = 5/6, vht) ?32 db 13 14.5 ? dbm phase noise 40 mhz crystal, integrated from 10 khz to 10 mhz ? 0.5 ? degrees tx power control dynamic range ? 10 ? ? db closed loop tx power variation at highest power level setting across full-temperature and voltage range. applies across 10 to 20 dbm output power range. ??2.0db carrier suppression ? 15 ? ? dbc gain control step ? ? 0.25 ? db return loss zo = 50 ? ?6?db
document number: 002-15054 rev. *i page 74 of 94 advance cyw43570 16. internal regulator electrical specifications note: values in this data sheet are design goals and are subject to change based on the results of device characterization. functional operation is not guarant eed outside of the specification limits provided in this section. 16.1 core buck switching regulator table 33. core buck switching regulator (cbuck) specifications specification notes min typ max units input supply voltage (dc) dc voltage r ange inclusive of disturbances. 3.0 3.3 3.6 a a. voltages up to 6.0v for up to 10 seconds, cumulative duration, over the lifetime of the devic e are allowed. voltages as high as 5.5v for up to 250 seconds, cumulative duration, over t he lifetime of the device are allowed. v pwm mode switching frequency ccm, load > 100 ma vbat = 3.6v 2.8 4 5.2 mhz pwm output current ? ? ? 600 ma output current limit ? ? 1400 ? ma output voltage range pro grammable, 30 mv steps default = 1.35v 1.2 1.35 1.5 v pwm output voltage dc accuracy includes load and line regulation. forced pwm mode ?4 ? 4 % pwm ripple voltage, static meas ure with 20 mhz bandwidth limit. static load. max ripple based on vbat = 3.6v, vout = 1.35v, fsw = 4 mhz, 2.2 h inductor l > 1.05 h, cap + board total-esr < 20 m ? , c out > 1.9 f, esl<200ph ?720mvpp pwm mode peak efficiency peak efficiency at 200 ma load 78 86 ? % pfm mode efficiency 10 ma load current 70 81 ? % start-up time from power down vio already on and steady. time from reg_on rising edge to cldo reaching 1.2v ??850 s external inductor 0806 size, 30%, 0.11 25% ohms ? 2.2 ? h external output capacit or ceramic, x5r, 0402, esr <30 m ? at 4 mhz, 20%, 6.3v 2.0 b b. minimum capacitor value refers to the re sidual capacitor value after taking into ac count the part-to-part tolerance, dc-bias, temperature, and aging. 4.7 10 c c. total capacitance includes those connected at the far end of the active load. f external input capacitor for sr_vddbatp5v pin, ceramic, x5r, 0603, esr < 30 m ? at 4 mhz, 20%, 6.3v, 4.7 f 0.67 b 4.7 ? f input supply voltage ramp-up time 0v to 3.3v 40 ? ? s
document number: 002-15054 rev. *i page 75 of 94 advance cyw43570 16.2 2.5v ldo (btldo2p5) table 34. btldo2p5 specifications specification notes min typ max units input supply voltage min = 2.5v + 0.2v = 2.7v. dropout voltage requirement must be met under maximum load for performance specifications. 3.0 3.3 3.6 a a. voltages up to 6.0v for up to 10 seconds, cumulative duration, over the lifetime of the devic e are allowed. voltages as high as 5.5v for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. v nominal output voltage default = 2.5v. ? 2.5 ? v output voltage programmability range 2.2 2.5 2.8 v accuracy at any step (including line/load regulation), load > 0.1 ma. ?5 ? 5 % dropout voltage at maximum load. ? ? 200 mv output current ? 0.1 ? 70 ma quiescent current no load. ? 8 16 a maximum load at 70 ma. ? 660 700 a leakage current power-down mode. ? 1.5 5 ? a line regulation v in from (v o + 0.2v) to 3.6v, maximum load. ??3.5mv/v load regulation load from 1 ma to 70 ma, v in = 3.6v. ??0.3mv/ma psrr v in v o + 0.2v, v o = 2.5v, c o = 2.2 f, maximum load, 100 hz to 100 khz. 20 ? ? db ldo turn-on time chip already powered up. ? ? 150 s in-rush current v in = v o + 0.15v to 3.6v, c o = 2.2 f, no load. ? ? 250 ma external output capacitor, c o ceramic, x5r, 0402, (esr: 5?240 m ? ), 10%, 10v 0.7 b b. the minimum value refers to the residual capacitor value after taking into account part-to-part tolerance, dc-bias, temperatu re, and aging. 2.2 2.64 f external input capacitor for sr_v ddbata5v pin (shared with bandgap) ceramic, x5r, 0402, (esr: 30?200 m ? ), 10%, 10v. not needed if sharing vbat 4.7 f capacitor with sr_vddbatp5v. ?4.7? f
document number: 002-15054 rev. *i page 76 of 94 advance cyw43570 16.3 cldo table 35. cldo specifications specification notes min typ max units input supply voltage, v in min = 1.2 + 0.15v = 1.35v dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 v output current ? 0.2 ? 300 ma output voltage, v o programmable in 25 mv steps. default = 1.2.v 1.1 1.2 1.275 v dropout voltage at max load ? ? 150 mv output voltage dc accuracy includes line/load regulation ?4 ? +4 % quiescent current no load ? 24 ? a 300 ma load ? 2.1 ? ma line regulation v in from (v o + 0.15v) to 1.5v, maximum load??5mv/v load regulation load from 1 ma to 300 ma ? 0.02 0.05 mv/ma leakage current power down ? ? 20 a bypass mode ? 1 3 a psrr @1 khz, vin 1.35v, c o = 4.7 f 20??db start-up time of pmu vio up and steady. time from the reg_on rising edge to the cldo reaching 1.2v. ? ? 700 s ldo turn-on time ldo turn-on time when rest of the chip is up ? 140 180 s external output capacitor, c o total esr: 5?240 m ? 1.32 a a. minimum capacitor value refers to the residual capacitor val ue after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 4.7 ? f external input capacitor only use an external input capacitor at the vdd_ldo pin if it is not supplied from cbuck output. ?12.2 f
document number: 002-15054 rev. *i page 77 of 94 advance cyw43570 16.4 lnldo table 36. lnldo specifications specification notes min typ max units input supply voltage, vin min = 1.2v o + 0.15v = 1.35v dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 v output current ? 0.1 ? 150 ma output voltage, v o programmable in 25 mv steps. default = 1.2v 1.1 1.2 1.275 v dropout voltage at maximum load ? ? 150 mv output voltage dc accuracy includes line/load regulation ?4 ? +4 % quiescent current no load ? 44 ? a max load ? 970 990 a line regulation v in from (v o + 0.1v) to 1.5v, max load ? ? 5 mv/v load regulation load from 1 ma to 150 ma ? 0.02 0.05 mv/ma leakage current power-down ? ? 10 a output noise @30 khz, 60?150 ma load c o = 2.2 f @100 khz, 60?150 ma load c o = 2.2 f ? ? 60 35 nv/rt hz nv/rt hz psrr @ 1khz, input > 1.35v, c o = 2.2 f, v o = 1.2v 20 ? ? db ldo turn-on time ldo turn-on time when rest of chip is up ? 140 180 s external output capacitor, c o total esr (trace/capacitor): 5?240 m ? 0.5 a a. minimum capacitor value refers to the re sidual capacitor value after taking into ac count the part-to-part tolerance, dc-bias, temperature, and aging. 2.2 4.7 f external input capacitor only use an external input capacitor at the vdd_ldo pin if it is not supplied from cbuck output. total esr (trace/capacitor): 30?200 m ? ? 1 2.2 f
document number: 002-15054 rev. *i page 78 of 94 advance cyw43570 17. system power consumption 17.1 wlan current consumption note: values in this data sheet are design goals and are subject to change based on the results of de vice characterization. unless otherwise stated, these values apply for the conditions specified in table 23 . the wlan current consumption measurements are shown in ta b l e 3 7 . all values in ta b l e 3 7 are with the bluetooth core in reset. . table 37. typical wlan power consumption mode bandwidth (mhz) band (ghz) v bat = v io = 3.3v (ma) off a ? ? 0.07 sleep b ??0.3 ieee power save, wowl mode, dtim 1 1 rx core c 20 2.4 3.87 ieee power save, wowl mode, dtim 3 1 rx core c 20 2.4 1.42 ieee power save, wowl mode, dtim 1 1 rx core c 20 5 2.34 ieee power save, wowl mode, dtim 3 1 rx core c 20 5 0.98 ieee power save, wowl mode, dtim 1 1 rx core c 40 5 2.65 ieee power save, wowl mode, dtim 3 1 rx core c 40 5 1.07 ieee power save, wowl mode, dtim 1 1 rx core c 80 5 3.13 ieee power save, wowl mode, dtim 3 1 rx core c 80 5 1.14 ieee power save, dtim 1 1 rx core c, d 20 2.4 8 ieee power save, dtim 3 1 rx core c, d 20 2.4 6.1 ieee power save, dtim 1 1 rx core c, d 20 5 7 ieee power save, dtim 3 1 rx core c, d 20 5 5.7 ieee power save, dtim 1 1 rx core c, d 40 5 7.2 ieee power save, dtim 3 1 rx core c, d 40 5 5.8 ieee power save, dtim 1 1 rx core c, d 80 5 7.3 ieee power save, dtim 3 1 rx core c, d 80 5 5.8 active modes transmit rate 11 (at measured power/core = 18.5 dbm) 20 2.4 358 mcs8, nss 1 (at measured power/core = 14 dbm) 20 2.4 250 mcs8, nss 2 (at measured power/core = 14 dbm) 20 2.4 470 mcs7, sgi (at measured power/core = 15 dbm) 20 5 302 mcs15, sgi (at measured power/core = 15 dbm) 20 5 543 mcs7 (at measured power/core = 17 dbm) 40 5 332 mcs9, nss 1 (at measured power/core = 14.5 dbm) 40 5 322 mcs9, nss 2 (at measured power/core = 14.5 dbm) 40 5 590 mcs9, nss 1 (at measured power/core = 13 dbm) 80 5 350 mcs9, nss 2 (at measured power/core = 13 dbm) 80 5 620 receive 1 mbps, 1 rx core 20 2.4 79 1 mbps, 2 rx cores 20 2.4 97 mcs7, ht20 1 rx core e 20 2.4 80 mcs7, ht20 2 rx cores e 20 2.4 99 mcs15, ht20 e 20 2.4 110
document number: 002-15054 rev. *i page 79 of 94 advance cyw43570 crs 1 rx core f 20 2.4 75 crs 2 rx cores f 20 2.4 93 receive mcs7, sgi 1 rx core e 20 5 89 receive mcs7, sgi 2 rx cores e 20 5 112 receiver mcs15, sgi e 20 5 125 crs 1 rx core f 20 5 80 crs 2 rx cores f 20 5 102 receive mcs 7, sgi 1 rx core e 40 5 110 receive mcs 7, sgi 2 rx cores e 40 5 143 receive mcs 15, sgi e 40 5 170 crs 1 rx core f 40 5 94 crs 2 rx cores f 40 5 125 receive mcs9, nss 1, sgi e 80 5 150 receive mcs9, nss 1, sgi 2 rx cores e 80 5 202 receive mcs9, nss 2, sgi e 80 5 220 crs 1 rx core f 80 5 115 crs 2 rx cores f 80 5 165 a. wl_reg_on, bt_reg_on low, no vddio. b. idle, not associated, or inter-beacon. c. beacon interval = 102.4 ms. beacon duration = 1 ms @1 mbps. average current over three dtim intervals. d. measurements were done on the broadcom brix platform. e. duty cycle is 100%. carrier sense (cs) detect/packet receive. f. carrier sense (cca) wh en no carrier is present. table 37. typical wlan power consumption (cont.) mode bandwidth (mhz) band (ghz) v bat = v io = 3.3v (ma)
document number: 002-15054 rev. *i page 80 of 94 advance cyw43570 17.2 bluetooth current consumption the bluetooth current consumpt ion measurements are listed in table 38 . note: the wlan core is in reset (wl_reg_on = low) for all measurements provided in table 38 . the bt current consumption numbers are measured based on: ? tgfsk tx output power = 12 dbm. ? vbat at 3.3v ? vio at 3.3v table 38. bluetooth current consumption operating mode vbat = vio = 3.3v (ma) sleep with external lpos 1.0 standard 1.28s inquiry scan 1.2 standard r1 page and 1.28s inquiry scan 1.3 500 ms sniff att = 4 master 1.2 500 ms sniff att = 4 slave 1.2 dm1/dh1 master tx/rx 25.5 dm3/dh3 master tx/rx 30.9 dm5/dh5 master tx/rx 31.8 3dh1 master tx/rx 23.2 3dh5 master tx/rx 29.5 3dh5 slave tx/rx 29.3 hv3 master (500 ms sniff) 11.7 2ev3 master (500 ms sniff) 8.4 hv3 slave r1 page and 2.56s inquiry scan 11.9 transmit 100% on maximum op bdr 49.8 receive 100% on 17.4 passive scan 1.28s 1.2 adv unconnectable 1.00s 1.1 adv connectable undirected 1.00s 1.1 connected 1.00s interval master 1.1
document number: 002-15054 rev. *i page 81 of 94 advance cyw43570 18. interface timing an d ac characteristics 18.1 pci express interface parameters table 39. pci express interface parameters parameter symbol comments min. typ. max. unit general baud rate bps ? ? 5 ? gbaud reference clock amplitude vref lvpecl, ac coupled 1 ? ? v receiver differential termination zrx-diff-dc differential termination 80 100 120 ? dc impedance zrx-dc dc common-mode impedance 40 50 60 ? powered down termination (pos) zrx-high-imp-dc-pos power-down or reset high impedance 100k ? ? ? powered down termination (neg) zrx-high-imp-dc-neg power-down or reset high impedance 1k ? ? ? input voltage vrx-diffp-p ac coupled, differential p-p 175??mv jitter tolerance trx-eye minimum receiver eye width 0.4??ui differential return loss rlrx-diff differential return loss 10 ? ? db common-mode return loss rlrx-cm common-mode return loss 6 ? ? db unexpected electrical idle enter detect threshold integration time trx-idel-det-diff- entertime an unexpected electrical idle must be recognized no longer than this time to signal an unexpected idle condition. ??10ms signal detect threshold vrx-idle-det-diffp-p electrical idle detect threshold 65 ? 175 mv transmitter output voltage vtx-diffp-p differential p-p, program- mable in 16 steps 0.8 ? 1200 mv output voltage rise time vtx-rise 20% to 80% 0.125 (2.5 gt/s) 0.15 (5 gt/s) ??ui output voltage fall time vtx-fall 80% to 20% 0.125 (2.5 gt/s) 0.15 (5 gt/s) ??ui rx detection voltage swing vtx-rcv-detect the amount of voltage change allowed during receiver detection. ? ? 600 mv tx ac peak common- mode voltage (5 gt/s) vtx-cm-ac-pp tx ac common mode voltage (5 gt/s) ? ? 100 mv tx ac peak common- mode voltage (2.5 gt/s) vtx-cm-ac-p tx ac common mode voltage (2.5 gt/s) ??20mv absolute delta of dc common-model voltage during l0 and electrical idle vtx-cm-dc-active- idle-delta absolute delta of dc common-model voltage during l0 and electrical idle. 0 ? 100 mv
document number: 002-15054 rev. *i page 82 of 94 advance cyw43570 absolute delta of dc common-model voltage between d+ and d- vtx-cm-dc-line-delta dc offset between d+ and d- 0?25mv electrical idle differential peak output voltage vtx-idle-diff-ac-p peak -to-peak voltage 0 ? 20 mv tx short circuit current itx-short current limit when tx output is shorted to ground. ??90ma dc differential tx termi- nation ztx-diff-dc low impedance defined during signaling (parameter is captured for 5.0 ghz by rltx-diff) 80 ? 120 ? differential return loss rltx-diff differential return loss 10 (min) for 0.05: 1.25 ghz ??db common-mode return loss rltx-cm common-mode return loss 6 ? ? db tx eye width ttx-eye minimum tx eye width 0.75 ? ? ui table 39. pci express interface parameters (cont.) parameter symbol comments min. typ. max. unit
document number: 002-15054 rev. *i page 83 of 94 advance cyw43570 19. power-up sequence and timing 19.1 sequencing of reset and regulator control signals the cyw43570 has two signals that allow the host to control powe r consumption by enabling or di sabling the bluetooth, wlan, and internal regulator blocks. these signals are described below. additionally, diagrams are provi ded to indicate proper sequencing of the signals for various operational states (see figure 26 , figure 27 , figure 28 and figure 29 ). the timing values indicated are minimum required values; longer delays are also acceptable. 19.1.1 description of control signals wl_reg_on : used by the pmu to power up the wlan section. it is also or-gated with the bt_r eg_on input to control the internal cyw43570 regulators. when this pin is high, the regulat ors are enabled and the wlan section is out of reset. when this pin is low the wlan section is in rese t. if both the bt_reg_on and wl_reg_on pins are low, the regulators are disabled. bt_reg_on : used by the pmu (or-gated with wl_reg_on) to power up the internal cyw43570 regulators. if both the bt_reg_on and wl_reg_on pins are low, the regulators are disa bled. when this pin is low and wl_reg_on is high, the bt section is in reset. note: for both the wl_reg_on and bt_reg _on pins, there should be at least a 10 ms time delay between consecutive toggles (where both signals have been driven low). this is to allow time for th e cbuck regulator to discharge. if this delay is not followed, then there may be a vddio in-rush current on the or der of 36 ma during the next pmu cold start. the cyw43570 has an internal power-on reset (por) circuit. the de vice will be held in reset for a maximum of 110 ms after vddc and vddio have both passed the por threshold. vbat should not rise 10%?90% faster than 40 microseconds. vbat should be up before or at the same time as vddio. vddio should not be present first or be held high before vbat is high.
document number: 002-15054 rev. *i page 84 of 94 advance cyw43570 19.1.2 control signal timing diagrams figure 26. wlan = on, bluetooth = on figure 27. wlan = off, bluetooth = off 32.678 khz sleep clock vbat* vddio wl_reg_on bt_reg_on high is 90% of vbat and low is 10% of vbat. 100 ms *notes: 1. vbat should not rise 10%?90% faster than 40 microseconds. 2. vbat should be up before or at the same time as vddio. vddi o should not be present first or be held high before vbat is high . 3. reset control signal timing for warm boot (high/low/high on reg_on) is 100 ms and for cold power-on (low/high) is 10 ms. vbat* vddio wl_reg_on bt_reg_on 32.678 khz sleep clock *notes: 1. vbat should not rise 10%?90% faster than 40 microseconds. 2. vbat should be up before or at the same time as vddio. vddio should not be present first or be held high before vbat is high .
document number: 002-15054 rev. *i page 85 of 94 advance cyw43570 figure 28. wlan = on, bluetooth = off figure 29. wlan = off, bluetooth = on vbat* vddio wl_reg_on bt_reg_on high is 90% of vbat and low is 10% of vbat. 100 ms 32.678 khz sleep clock *notes: 1. vbat should not rise 10%?90% faster than 40 microseconds. 2. vbat should be up before or at the same time as vddio. vddio should not be present first or be held high before vbat is high . 3. reset control signal timing for warm boot (high/low/high on reg_on) is 100 ms and for cold power-on (low/high) is 10 ms. vbat* vddio wl_reg_on bt_reg_on high is 90% of vbat and low is 10% of vbat. 100 ms 32.678 khz sleep clock *notes: 1. vbat should not rise 10%?90% faster than 40 microseconds. 2. vbat should be up before or at the same time as vddio. v ddio should not be present first or be held high before vbat is high . 3. reset control signal timing for warm boot (high/low/high on reg_on) is 100 ms and for cold power-on (low/high) is 10 ms.
document number: 002-15054 rev. *i page 86 of 94 advance cyw43570 figure 30 shows the wlan boot sequence from power-up to firmware download. figure 30. wlan boot sequence < 850 s after 8 ms the reference clock is assumed to be up. access to pll registers is possible. 8 ms < 4 ms < 104 ms after a fixed delay following internal por and wl_reg_on going high, the device responds to host f0 (address 0x14) reads. vddio wl_reg_on vddc (from internal pmu) internal por device requests for reference clock host interaction: host polls f0 (address 0x14) until it reads a predefined pattern. host sets wake-up-wlan bit and waits 8 ms, the maximum time for reference clock availability. after 8 ms, host programs pll registers to set crystal frequency host downloads code.** chip active interrupt is asserted after the pll locks vbat* *notes: 1. vbat should not rise 10%?90% faster than 40 microseconds. 2. vbat should be up before or at the same time as vddio . vddio should not be present first or be held high before vbat is high. 3. for timing information of the host interaction (after asserting wl_reg_on) to be ready for firmware download is typically 124 ms, including por. 4. wi-fi fw download depends on the system performance and memory available . typically, the firmware download on a fc19 linux pc is 102 ms. **note: 1. host download code is typically ~102 ms, but it also depends on the size of the firmware . after the firmware download is complete, it is recommended to wait an additional 250 ms before host can issue control commands to a dongle.
document number: 002-15054 rev. *i page 87 of 94 advance cyw43570 figure 31 shows the bluetooth boot-up sequence from power-up to firmware download. figure 31. bluetooth boot-up sequence vbatt/vddio bt_usb_dp bt_reg_on t1 notes: ?? t1: ? reset ? control ? signal ? timing ? ~100 ? ms. t2: ? bt ? por ? and ? fw ? rom ? boot ? time, ? before ? bt ? enables ? usb ? d+ ? pull \ up ? to ? connect ? the ? device ? to ? the ? host, ?? ranges ? from ? 100 ? ms ? (rom ? boot) ? to ? 250 ? ms ? (depends ? on ? the ? size ? of ? fw ? download, ? based ? on ? broadcom ? qualified ? bt ? sflash). t3: ? > ? 100 ? ms ? usb ? connection ? de \ bounce ? time ? on ? the ? host ? side. t5: ? > ? 10 ? ms ? host ? drives ? usb ? reset. t6: ? > ? 10 ? ms ? host ? sends ? usb ? sof ? packet. after ? t6: ? device ? is ? ready ? to ? communicate ? with ? the ? host. t2 t3 t5 t6 bt_usb_dn
document number: 002-15054 rev. *i page 88 of 94 advance cyw43570 20. package information 20.1 package thermal characteristics 20.2 junction temperature estimation and psi jt versus theta jc the package thermal characterization parameter psi jt ( ? jt ) yields a better estimation of actual junction temperature (t j ) than using the junction-to-case thermal resistance parameter theta jc ( ? jc ). the reason for this is that ? jc is based on the assumption that all the power is dissipated through the top surface of the package case . in actual applications, however, some of the power is diss ipated through the bottom and sides of the package. ? jt takes into account the power dissipated through the top, bottom, and sides of the package. the equation for calculating the device junction temperature is: t j = t t + p x ? jt where: t j = junction temperature at st eady-state condition (c) t t = package case top center temperatur e at steady-state condition (c) p = device power dissipation (watts) ? jt = package thermal characteri stics; no airflow (c/w) 20.3 environmental characteristics for environmental char acteristics data, see table 22 . table 40. package thermal characteristics a a. no heat sink, ta = 70c. this is an es timate, based on a 4-layer pcb that conforms to eia/jesd51?7 (101.6 mm 101.6 mm 1.6 mm) an d p = 1.53w continuous dissipation. characteristic value ? ja (c/w) (value in still air) 26.38 ? jb (c/w) 8.37 ? jc (c/w) 9.94 ? jt (c/w) 6.12 ? jb (c/w) 12.62 maximum junction temperature t j (c) 125 maximum power dissipation (w) 2.46
document number: 002-15054 rev. *i page 89 of 94 advance cyw43570 21. mechanical information figure 32. 242-ball packag e mechanical information
document number: 002-15054 rev. *i page 90 of 94 advance cyw43570 22. ordering information 23. additiona l information 23.1 acronyms and abbreviations in most cases, acronyms and abbreviations are defined on first use. for a comprehensive list of acronyms and other terms used in cypress documents, go to: http://www.cypre ss.com/glossary 23.2 references the references in this section may be used in conjunction with this document. note: cypress provides customer access to te chnical documentation and software through its cypress developer community and downloads and support site (see iot resources ). for cypress documents, replace the ?xx? in the document number wi th the largest number available in the repository to ensure th at you have the most current version of the document. 24. iot resources cypress provides a wealth of data at http://www.cypress.com /internet-things-iot to help you to select th e right iot device for your design, and quickly and effectively integrate the device into your design. cypress provides customer access to a wide range of information, including technical documentat ion, schematic diagrams, product bill of ma terials, pcb layout information, and soft ware updates. customers can acquire technica l documentation and soft ware from the cypress support community website ( http://community.cypress.com/ ). part number package description operating ambient temperature BCM43570KFFBG 242-ball fcbga (10 mm 10 mm, 0.4 mm pitch) dual-band 2.4 ghz and 5 ghz wlan + bluetooth 4.1 + edr 0c to +60c (32f to 140f) document (or item) name number source bluetooth mws coexistence 2.wire transport interface specification ? www.bluetooth.com pci express base specification v2.0. ? www.pcisig.com
document number: 002-15054 rev. *i page 91 of 93 advance cyw43570 document history document title: cyw43570 single-chip 5g wifi ieee 802.11ac 22 mac/baseband/ radio with integrated bluetooth 4.1 and edr document number: 002-15054 revision ecn orig. of change submission date description of change ** ? ? 04/02/2014 43570-ds100-r initial release *a ? ? 04/14/2014 43570-ds101-r updated: ? section 22. ordering information *b ? ? 07/02/2014 43570-ds102-r updated: ? table 18. pin list ? table 19. signal descriptions *c ? ? 07/11/2014 43570-ds103-r updated: ? table 37. typical wlan power consumption ? table 38. bluetooth ble and fm current consumption *d ? ? 07/29/2014 43570-ds104-r updated: ? table 5. power control pin description ? figure 5. startup signaling sequence ? table 6. spi-to-uart signal mapping ? figure 32. 242-ball package mechanical information ? pcm interface timing ? table 15. uart timing specifications ? figure 16. uart timing ? figure 32. 242-ball package mechanical information added: ? table 6. pcm-to-serial flash interface mapping *e ? ? 08/03/2015 43570-ds105-r updated: ? general description and features ? figure 1. functional block diagram for pc ie (wlan) and bt (usb 2.0) interfaces ? table 2. device interface support ? figure 2. cyw43570/e block diagram ? cyw43570/e pmu features ? uart/usb transport detection ? usb interface ? table 17. strapping options pcie ? table 20. bt gpio functions and strapping options ? table 24. bluetooth receiver rf specifications ? table 28. 2.4 ghz band general rf specifications ? table 29. wlan 2.4 ghz receiver pe rformance specifications through table 32. wlan 5 ghz transmitte r performance specifications ? table 37. typical wlan power consumption ? table 38. bluetooth current consumption ? bluetooth current consumption ? figure 26. wlan = on, bluetooth = on ? figure 27. wlan = off, bluetooth = off ? figure 28. wlan = on, bluetooth = off ? figure 29. wlan = off, bluetooth = on ? figure 30. wlan boot sequence ? table 40. package thermal characteristics added: ? figure 31. bluetooth boot-up sequence ? note: vbat is the main power supply (ranges from 3.0v to 3.6v) to the chip. *f ? ? 01/05/2016 43570-ds106-r updated: ? figure 1. functional block diagram for pcie (wlan) and bt (usb 2.0) interfaces ? spi/uart transport detection
document number: 002-15054 rev. *i page 92 of 93 advance cyw43570 *g ? ? 02/19/2016 43570-ds107-r updated: ? table 21. absolute maximum ratings ? table 23. recommended operating c onditions and dc characteristics ? table 33. core buck switching regulator (cbuck) specifications ? table ?ldo3p3 specifications? ? table 34. btldo2p5 specifications *h ? ? 03/10/2016 43570-ds108-r updated: ? section 13. dc characteristics ? table 33. core buck switching regulator (cbuck) specifications ? table 34. btldo2p5 specifications removed: ? table ?ldo3p3 specifications? *i 5491700 utsv 10/27/2016 updated to cypress template. added cypress part numbering scheme. document title: cyw43570 single-chip 5g wifi ieee 802.11ac 22 mac/baseband/ radio with integrated bluetooth 4.1 and edr document number: 002-15054
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